A Fast Emulation-Based NoC Prototyping Framework

Authors:
Yana E. Krasteva;Francisco Criado;Eduardo de la Torre;Teresa Riesgo
Affiliations:
-;-;-;-
Venue:
RECONFIG '08 Proceedings of the 2008 International Conference on Reconfigurable Computing and FPGAs
Year:
2008

Citing 0
Cited 8

A reconfigurable platform for evaluating the performance of QoS networks

Journal of Systems Architecture: the EUROMICRO Journal
Reconfigurable Networks on Chip: DRNoC architecture

Journal of Systems Architecture: the EUROMICRO Journal
A networks-on-chip emulation/verification framework

International Journal of High Performance Systems Architecture
CAFES: A framework for intrachip application modeling and communication architecture design

Journal of Parallel and Distributed Computing
DART: a programmable architecture for NoC simulation on FPGAs

NOCS '11 Proceedings of the Fifth ACM/IEEE International Symposium on Networks-on-Chip
Exploiting temporal decoupling to accelerate trace-driven NoC emulation

CODES+ISSS '11 Proceedings of the seventh IEEE/ACM/IFIP international conference on Hardware/software codesign and system synthesis
Enabling fast ASIP design space exploration: an FPGA-based runtime reconfigurable prototyper

VLSI Design
Exploiting binary translation for fast ASIP design space exploration on fpgas

DATE '12 Proceedings of the Conference on Design, Automation and Test in Europe

Quantified Score

Hi-index	0.00

Visualization

Abstract

This paper presents an embedded FPGA–based architecture to compute navigation trajectories along a harmonic potential. The goals and obstacles may be changed during computation. Large environments are split into blocks. This approach, together ...