Exploiting binary translation for fast ASIP design space exploration on fpgas

Authors:
Sebastiano Pomata;Paolo Meloni;Giuseppe Tuveri;Luigi Raffo;Menno Lindwer
Affiliations:
University of Cagliari;University of Cagliari;University of Cagliari;University of Cagliari;Intel Corp., Eindhoven
Venue:
DATE '12 Proceedings of the Conference on Design, Automation and Test in Europe
Year:
2012

Citing 8
Cited 1

Dynamic Binary Translation and Optimization

IEEE Transactions on Computers
Dynamic and Transparent Binary Translation

Computer
The Transmeta Code Morphing™ Software: using speculation, recovery, and adaptive retranslation to address real-life challenges

Proceedings of the international symposium on Code generation and optimization: feedback-directed and runtime optimization
MPARM: Exploring the Multi-Processor SoC Design Space with SystemC

Journal of VLSI Signal Processing Systems
A system-level framework for evaluating area/performance/power trade-offs of VLIW-based embedded systems

Proceedings of the 2005 Asia and South Pacific Design Automation Conference
FPGA-Accelerated Simulation Technologies (FAST): Fast, Full-System, Cycle-Accurate Simulators

Proceedings of the 40th Annual IEEE/ACM International Symposium on Microarchitecture
A Fast Emulation-Based NoC Prototyping Framework

RECONFIG '08 Proceedings of the 2008 International Conference on Reconfigurable Computing and FPGAs
Dynamically reconfigurable register file for a softcore VLIW processor

Proceedings of the Conference on Design, Automation and Test in Europe

ASAM: Automatic architecture synthesis and application mapping

Microprocessors & Microsystems

Quantified Score

Hi-index	0.00

Visualization

Abstract

Complex Application Specific Instruction-set Processors (ASIPs) expose to the designer a large number of degrees of freedom, posing the need for highly accurate and rapid simulation environments. FPGA-based emulators represent an alternative to software cycle-accurate simulators, preserving maximum accuracy and reasonable simulation times. The work presented in this paper aims at exploiting FPGA emulation within technology aware design space exploration of ASIPs. The potential speedup provided by reconfigurable logic is reduced by the overhead of RTL synthesis/implementation. This overhead can be mitigated by reducing the number of FPGA implementation processes, through the adoption of binary-level translation. Hereby we present a prototyping method that, given a set of candidate ASIP configurations, defines an overdimensioned ASIP architecture, capable of emulating all the design space points under evaluation. This approach is then evaluated with a design space exploration case study. Along with execution time, by coupling FPGA emulation with activity-based physical modeling, we can extract area/power/energy figures.