Modeling cost/performance of a parallel computer simulator
ACM Transactions on Modeling and Computer Simulation (TOMACS)
CoWare—a design environment for heterogenous hardware/software systems
EURO-DAC '96/EURO-VHDL '96 Proceedings of the conference on European design automation
Hardware synthesis from C/C++ models
DATE '99 Proceedings of the conference on Design, automation and test in Europe
Proceedings of the 37th Annual Design Automation Conference
LOTTERYBUS: a new high-performance communication architecture for system-on-chip designs
Proceedings of the 38th annual Design Automation Conference
Complete Computer System Simulation: The SimOS Approach
IEEE Parallel & Distributed Technology: Systems & Technology
A Comparison of Five Different Multiprocessor SoC Bus Architectures
DSD '01 Proceedings of the Euromicro Symposium on Digital Systems Design
A simulation methodology for reliability analysis in multi-core SoCs
GLSVLSI '06 Proceedings of the 16th ACM Great Lakes symposium on VLSI
A fast HW/SW FPGA-based thermal emulation framework for multi-processor system-on-chip
Proceedings of the 43rd annual Design Automation Conference
Multi-processor operating system emulation framework with thermal feedback for systems-on-chip
Proceedings of the 17th ACM Great Lakes symposium on VLSI
A lightweight parallel java execution environment for embedded multiprocessor systems-on-chip
Proceedings of the 17th ACM Great Lakes symposium on VLSI
HW-SW emulation framework for temperature-aware design in MPSoCs
ACM Transactions on Design Automation of Electronic Systems (TODAES)
The Impact of Higher Communication Layers on NoC Supported MP-SoCs
NOCS '07 Proceedings of the First International Symposium on Networks-on-Chip
CATS: cycle accurate transaction-driven simulation with multiple processor simulators
Proceedings of the conference on Design, automation and test in Europe
Efficient event-driven simulation of parallel processor architectures
SCOPES '07 Proceedingsof the 10th international workshop on Software & compilers for embedded systems
Cache coherency communication cost in a NoC-based MPSoC platform
Proceedings of the 20th annual conference on Integrated circuits and systems design
Automatic generation of hardware dependent software for MPSoCs from abstract system specifications
Proceedings of the 2008 Asia and South Pacific Design Automation Conference
Reliability-aware design for nanometer-scale devices
Proceedings of the 2008 Asia and South Pacific Design Automation Conference
Invited paper: Network-on-Chip design and synthesis outlook
Integration, the VLSI Journal
Multi-granularity sampling for simulating concurrent heterogeneous applications
CASES '08 Proceedings of the 2008 international conference on Compilers, architectures and synthesis for embedded systems
Partial order method for timed simulation of system-level MPSoC designs
Proceedings of the 2009 Asia and South Pacific Design Automation Conference
Fast and accurate performance simulation of embedded software for MPSoC
Proceedings of the 2009 Asia and South Pacific Design Automation Conference
Memory subsystem simulation in software TLM/T models
Proceedings of the 2009 Asia and South Pacific Design Automation Conference
Energy-optimal synchronization primitives for single-chip multi-processors
Proceedings of the 19th ACM Great Lakes symposium on VLSI
Power-Aware Bus Coscheduling for Periodic Realtime Applications Running on Multiprocessor SoC
Transactions on High-Performance Embedded Architectures and Compilers II
A platform-based design framework for joint SW/HW multiprocessor systems design
Journal of Systems Architecture: the EUROMICRO Journal
A compositional modelling framework for exploring MPSoC systems
CODES+ISSS '09 Proceedings of the 7th IEEE/ACM international conference on Hardware/software codesign and system synthesis
A standby-sparing technique with low energy-overhead for fault-tolerant hard real-time systems
CODES+ISSS '09 Proceedings of the 7th IEEE/ACM international conference on Hardware/software codesign and system synthesis
Cycle count accurate memory modeling in system level design
CODES+ISSS '09 Proceedings of the 7th IEEE/ACM international conference on Hardware/software codesign and system synthesis
Fast and accurate processor models for efficient MPSoC design
ACM Transactions on Design Automation of Electronic Systems (TODAES)
MEMOCODE'09 Proceedings of the 7th IEEE/ACM international conference on Formal Methods and Models for Codesign
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
An integrated thermal estimation framework for industrial embedded platforms
Proceedings of the 20th symposium on Great lakes symposium on VLSI
Proceedings of the 20th symposium on Great lakes symposium on VLSI
Performance evaluation of concurrently executing parallel applications on multi-processor systems
SAMOS'09 Proceedings of the 9th international conference on Systems, architectures, modeling and simulation
Evaluating the impact of task migration in multi-processor systems-on-chip
SBCCI '10 Proceedings of the 23rd symposium on Integrated circuits and system design
Exploring memory organization in virtual MP-SoC platforms
SBCCI '10 Proceedings of the 23rd symposium on Integrated circuits and system design
Exploring programming model-driven QoS support for NoC-based platforms
CODES/ISSS '10 Proceedings of the eighth IEEE/ACM/IFIP international conference on Hardware/software codesign and system synthesis
CODES/ISSS '10 Proceedings of the eighth IEEE/ACM/IFIP international conference on Hardware/software codesign and system synthesis
Platform modeling for exploration and synthesis
Proceedings of the 2010 Asia and South Pacific Design Automation Conference
System-level development of embedded software
Proceedings of the 2010 Asia and South Pacific Design Automation Conference
Thermal-aware system analysis and software synthesis for embedded multi-processors
Proceedings of the 48th Design Automation Conference
Mapping of applications to MPSoCs
CODES+ISSS '11 Proceedings of the seventh IEEE/ACM/IFIP international conference on Hardware/software codesign and system synthesis
System-level power and timing variability characterization to compute thermal guarantees
CODES+ISSS '11 Proceedings of the seventh IEEE/ACM/IFIP international conference on Hardware/software codesign and system synthesis
Convex-based thermal management for 3D MPSoCs using DVFS and variable-flow liquid cooling
PATMOS'11 Proceedings of the 21st international conference on Integrated circuit and system design: power and timing modeling, optimization, and simulation
PRO3D: programming for future 3D manycore architectures
Proceedings of the 2012 Interconnection Network Architecture: On-Chip, Multi-Chip Workshop
Proceedings of the ACM/SIGDA international symposium on Field Programmable Gate Arrays
ACM Transactions on Embedded Computing Systems (TECS)
Proceedings of the 2012 Workshop on Rapid Simulation and Performance Evaluation: Methods and Tools
ARCS'10 Proceedings of the 23rd international conference on Architecture of Computing Systems
ARCS'12 Proceedings of the 25th international conference on Architecture of Computing Systems
Development process for clusters on a reconfigurable chip
Computers and Electrical Engineering
Fast architecture evaluation of heterogeneous MPSoCs by host-compiled simulation
Proceedings of the 15th International Workshop on Software and Compilers for Embedded Systems
Automatic extraction of multi-objective aware pipeline parallelism using genetic algorithms
Proceedings of the eighth IEEE/ACM/IFIP international conference on Hardware/software codesign and system synthesis
HyCoS: hybrid compiled simulation of embedded software with target dependent code
Proceedings of the eighth IEEE/ACM/IFIP international conference on Hardware/software codesign and system synthesis
Integration, the VLSI Journal
Predictability for timing and temperature in multiprocessor system-on-chip platforms
ACM Transactions on Embedded Computing Systems (TECS) - Special section on ESTIMedia'12, LCTES'11, rigorous embedded systems design, and multiprocessor system-on-chip for cyber-physical systems
Proceedings of the 7th International Conference on Body Area Networks
Multi-objective aware extraction of task-level parallelism using genetic algorithms
DATE '12 Proceedings of the Conference on Design, Automation and Test in Europe
Exploiting binary translation for fast ASIP design space exploration on fpgas
DATE '12 Proceedings of the Conference on Design, Automation and Test in Europe
A hybrid HW-SW approach for intermittent error mitigation in streaming-based embedded systems
DATE '12 Proceedings of the Conference on Design, Automation and Test in Europe
An automatic energy consumption characterization of processors using ArchC
Journal of Systems Architecture: the EUROMICRO Journal
Physical Security Evaluation at an Early Design-Phase: A Side-Channel Aware Simulation Methodology
Proceedings of International Workshop on Engineering Simulations for Cyber-Physical Systems
The COMPLEX methodology for UML/MARTE Modeling and design space exploration of embedded systems
Journal of Systems Architecture: the EUROMICRO Journal
Journal of Electronic Testing: Theory and Applications
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Technology is making the integration of a large number of processors on the same silicon die technically feasible. These multi-processor systems-on-chip (MP-SoC) can provide a high degree of flexibility and represent the most efficient architectural solution for supporting multimedia applications, characterized by the request for highly parallel computation. As a consequence, tools for the simulation of these systems are needed for the design stage, with the distinctive requirement of simulation speed, accuracy and capability to support design space exploration. We developed a complete simulation platform for a MP-SoC called MP-ARM, based on SystemC as modelling and simulation environment, and including models for processors, the AMBA bus compliant communication architecture, memory models and support for parallel programming. A fully operating linux version for embedded systems has been ported on this platform, and a cross-toolchain has been developed as well. Our MP simulation environment turns out to be a powerful tool for the MP-SOC design stage. As an example thereof, we use our tool to evaluate the impact on system performance of architectural parameters and of bus arbitration policies, showing that the effectiveness of a particular system configuration strongly depends on the application domain and the generated traffic profile.