SSIM: a software levelized compiled-code simulator
DAC '87 Proceedings of the 24th ACM/IEEE Design Automation Conference
A two-state methodology for RTL logic simulation
Proceedings of the 36th annual ACM/IEEE Design Automation Conference
DATE '00 Proceedings of the conference on Design, automation and test in Europe
Proceedings of the 38th annual Design Automation Conference
A universal technique for fast and flexible instruction-set architecture simulation
Proceedings of the 39th annual Design Automation Conference
MPARM: Exploring the Multi-Processor SoC Design Space with SystemC
Journal of VLSI Signal Processing Systems
Combining simulation and formal methods for system-level performance analysis
Proceedings of the conference on Design, automation and test in Europe: Proceedings
An integrated open framework for heterogeneous MPSoC design space exploration
Proceedings of the conference on Design, automation and test in Europe: Proceedings
Ultra fast cycle-accurate compiled emulation of inorder pipelined architectures
SAMOS'05 Proceedings of the 5th international conference on Embedded Computer Systems: architectures, Modeling, and Simulation
Processor Description Languages
Processor Description Languages
A holistic approach for tightly coupled reconfigurable parallel processors
Microprocessors & Microsystems
Hierarchical power management for adaptive tightly-coupled processor arrays
ACM Transactions on Design Automation of Electronic Systems (TODAES) - Special section on adaptive power management for energy and temperature-aware computing systems
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In this paper we present a new approach for generating high-speed optimized event-driven instruction set level simulators for adaptive massively parallel processor architectures. The simulator generator is part of a methodology for the systematic mapping, evaluation, and exploration of massively parallel processor architectures that are designed for special purpose applications in the world of embedded computers. The generation of high-speed cycle-accurate simulators is of utmost importance here, because they are directly used both for parallel processor architecture debugging and evaluation purposes, as well as during time-consuming architecture/compiler co-exploration. We developed a modeling environment which automatically generates a C++ simulation model either from a graphical input or directly from an XML-based architecture description. Here, we focus on the underlying event-driven simulation model and present our modeling environment, in particular the features of the graphical parallel processor architecture editor and the automatic instruction set level simulator generator. Finally, in a case-study, we demonstrate the pertinence of our approach by simulating different processor arrays. The superior performance of the generated simulators compared to existing simulators and simulator generation approaches is shown.