Highly parallel computing (2nd ed.)
Highly parallel computing (2nd ed.)
IEEE Transactions on Computers - Special issue on cache memory and related problems
Using MPI (2nd ed.): portable parallel programming with the message-passing interface
Using MPI (2nd ed.): portable parallel programming with the message-passing interface
Interconnection Networks: An Engineering Approach
Interconnection Networks: An Engineering Approach
Performance Optimization for Large Scale Computing: The Scalable VAMPIR Approach
ICCS '01 Proceedings of the International Conference on Computational Science-Part II
MPARM: Exploring the Multi-Processor SoC Design Space with SystemC
Journal of VLSI Signal Processing Systems
An automated exploration framework for FPGA-based soft multiprocessor systems
CODES+ISSS '05 Proceedings of the 3rd IEEE/ACM/IFIP international conference on Hardware/software codesign and system synthesis
A fast HW/SW FPGA-based thermal emulation framework for multi-processor system-on-chip
Proceedings of the 43rd annual Design Automation Conference
PDP '08 Proceedings of the 16th Euromicro Conference on Parallel, Distributed and Network-Based Processing (PDP 2008)
Invited paper: Network-on-Chip design and synthesis outlook
Integration, the VLSI Journal
MPI-Based Adaptive Task Migration Support on the HS-Scale System
ISVLSI '08 Proceedings of the 2008 IEEE Computer Society Annual Symposium on VLSI
International Journal of Parallel Programming
MPLEM: An 80-processor FPGA Based Multiprocessor System
FCCM '08 Proceedings of the 2008 16th International Symposium on Field-Programmable Custom Computing Machines
SoC-MPI: A Flexible Message Passing Library for Multiprocessor Systems-on-Chips
RECONFIG '08 Proceedings of the 2008 International Conference on Reconfigurable Computing and FPGAs
AHS '09 Proceedings of the 2009 NASA/ESA Conference on Adaptive Hardware and Systems
Overview of FPGA-Based Multiprocessor Systems
RECONFIG '09 Proceedings of the 2009 International Conference on Reconfigurable Computing and FPGAs
rMPI: message passing on multicore processors with on-chip interconnect
HiPEAC'08 Proceedings of the 3rd international conference on High performance embedded architectures and compilers
Efficient OpenMP support and extensions for MPSoCs with explicitly managed memory hierarchy
Proceedings of the Conference on Design, Automation and Test in Europe
MPSoC Performance Analysis with Virtual Prototyping Platforms
ICPPW '10 Proceedings of the 2010 39th International Conference on Parallel Processing Workshops
Some computer organizations and their effectiveness
IEEE Transactions on Computers
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Reconfigurable MPSoCs (Multiprocessor System-on-Chip) could be viable for certain applications niche where the flexibility of FPGAs (Field-Programmable Gate Array) and software is needed, and a small number of units dismiss other silicon options. However, their design complexity is very high, and raises additional problems, i.e. the definition of a suitable programming model, an efficient memory organization, and the need for ways to optimize application performance. In this paper, we propose a complete development process, which addresses these problems by complementing the current SoC (System-on-Chip) development process with additional steps to support parallel programming and software optimization. This work explains systematically problems and solutions to achieve a FPGA-based MPSoC following our systematic flow and offering tools and techniques to develop parallel applications for such systems.