A lean FPGA soft processor built using a DSP block
Proceedings of the ACM/SIGDA international symposium on Field Programmable Gate Arrays
Development process for clusters on a reconfigurable chip
Computers and Electrical Engineering
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This paper presents an architecture and implementation details for MORA, a novel coarse grained reconfigurable processor for accelerating media processing applications. The MORA architecture involves a 2-D array of several such processors, to deliver low cost, high throughput performance in media processing applications. A distinguishing feature of the MORA architecture is the co-design of hardware architecture and low-level programming language throughout the design cycle. The implementation details for the single MORA processor, and benchmark evaluation using a cycle accurate simulator are presented.