Efficient Worst-Case Temperature Evaluation for Thermal-Aware Assignment of Real-Time Applications on MPSoCs

  • Authors:

  • Lars Schor;Iuliana Bacivarov;Hoeseok Yang;Lothar Thiele

  • Affiliations:

  • Computer Engineering and Networks Laboratory, ETH Zurich, Zurich, Switzerland 8092;Computer Engineering and Networks Laboratory, ETH Zurich, Zurich, Switzerland 8092;Computer Engineering and Networks Laboratory, ETH Zurich, Zurich, Switzerland 8092;Computer Engineering and Networks Laboratory, ETH Zurich, Zurich, Switzerland 8092

  • Venue:
  • Journal of Electronic Testing: Theory and Applications
  • Year:
  • 2013

Quantified Score

Hi-index 0.00

Visualization

Abstract

The reliability of multiprocessor system-on-chips (MPSoCs) is nowadays threatened by high chip temperatures leading to long-term reliability concerns and short-term functional errors. High chip temperatures might not only cause potential deadline violations, but also increase cooling costs and leakage power. Pro-active thermal-aware allocation and scheduling techniques that avoid thermal emergencies are promising techniques to reduce the peak temperature of an MPSoC. However, calculating the peak temperature of hundreds of design alternatives during design space exploration is time-consuming, in particular for unknown input patterns and data. In this paper, we address this challenge and present a fast analytic method to calculate a non-trivial upper bound on the maximum temperature of a multi-core real-time system with non-deterministic workload. The considered thermal model is able to address various thermal effects like heat exchange between neighboring cores and temperature-dependent leakage power. Afterwards, we integrate the proposed thermal analysis method into a design-space exploration framework to optimize the task to processing component assignment. Finally, we apply the proposed method in various case studies to explore thermal hot spots and to optimize the task to processing component assignment.