Wattch: a framework for architectural-level power analysis and optimizations
Proceedings of the 27th annual international symposium on Computer architecture
A static power model for architects
Proceedings of the 33rd annual ACM/IEEE international symposium on Microarchitecture
Design of High-Performance Microprocessor Circuits
Design of High-Performance Microprocessor Circuits
Proceedings of the 2002 IEEE/ACM international conference on Computer-aided design
Temperature-aware microarchitecture
Proceedings of the 30th annual international symposium on Computer architecture
Full chip leakage estimation considering power supply and temperature variations
Proceedings of the 2003 international symposium on Low power electronics and design
Leakage current reduction in CMOS VLSI circuits by input vector control
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Characterization and modeling of run-time techniques for leakage power reduction
IEEE Transactions on Very Large Scale Integration (VLSI) Systems - Nanoelectronic circuits and systems
New Generation of Predictive Technology Model for Sub-45nm Design Exploration
ISQED '06 Proceedings of the 7th International Symposium on Quality Electronic Design
Hotspot: acompact thermal modeling methodology for early-stage VLSI design
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Temperature and supply Voltage aware performance and power modeling at microarchitecture level
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Three-dimensional multiprocessor system-on-chip thermal optimization
CODES+ISSS '07 Proceedings of the 5th IEEE/ACM international conference on Hardware/software codesign and system synthesis
Statistical power profile correlation for realistic thermal estimation
Proceedings of the 2008 Asia and South Pacific Design Automation Conference
Thermal monitoring mechanisms for chip multiprocessors
ACM Transactions on Architecture and Code Optimization (TACO)
Temperature-aware scheduling and assignment for hard real-time applications on MPSoCs
Proceedings of the conference on Design, automation and test in Europe
Online work maximization under a peak temperature constraint
Proceedings of the 14th ACM/IEEE international symposium on Low power electronics and design
Energy-optimal dynamic thermal management for green computing
Proceedings of the 2009 International Conference on Computer-Aided Design
Thermal analysis of multiprocessor SoC applications by simulation and verification
ACM Transactions on Design Automation of Electronic Systems (TODAES)
Thermal aware task sequencing on embedded processors
Proceedings of the 47th Design Automation Conference
Dynamic thermal management for networked embedded systems under harsh ambient temperature variation
Proceedings of the 16th ACM/IEEE international symposium on Low power electronics and design
Energy-efficient real-time task scheduling with temperature-dependent leakage
Proceedings of the Conference on Design, Automation and Test in Europe
Temperature-aware idle time distribution for energy optimization with dynamic voltage scaling
Proceedings of the Conference on Design, Automation and Test in Europe
Thermally optimal stop-go scheduling of task graphs with real-time constraints
Proceedings of the 16th Asia and South Pacific Design Automation Conference
Leakage conscious DVS scheduling for peak temperature minimization
Proceedings of the 16th Asia and South Pacific Design Automation Conference
Thermal-aware global real-time scheduling and analysis on multicore systems
Journal of Systems Architecture: the EUROMICRO Journal
Throughput maximization for periodic real-time systems under the maximal temperature constraint
Proceedings of the 48th Design Automation Conference
Cool shapers: shaping real-time tasks for improved thermal guarantees
Proceedings of the 48th Design Automation Conference
Power profiling-guided floorplanner for thermal optimization in 3D multiprocessor architectures
PATMOS'11 Proceedings of the 21st international conference on Integrated circuit and system design: power and timing modeling, optimization, and simulation
Worst-case temperature analysis for different resource availabilities: a case study
PATMOS'11 Proceedings of the 21st international conference on Integrated circuit and system design: power and timing modeling, optimization, and simulation
Proceedings of the 20th International Conference on Real-Time and Network Systems
On the fundamentals of leakage aware real-time DVS scheduling for peak temperature minimization
Journal of Systems Architecture: the EUROMICRO Journal
Thermal Characterization of Test Techniques for FinFET and 3D Integrated Circuits
ACM Journal on Emerging Technologies in Computing Systems (JETC)
Predictability for timing and temperature in multiprocessor system-on-chip platforms
ACM Transactions on Embedded Computing Systems (TECS) - Special section on ESTIMedia'12, LCTES'11, rigorous embedded systems design, and multiprocessor system-on-chip for cyber-physical systems
System-level modeling of energy in TLM for early validation of power and thermal management
Proceedings of the Conference on Design, Automation and Test in Europe
Temperature-aware idle time distribution for leakage energy optimization
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
TempoMP: integrated prediction and management of temperature in heterogeneous MPSoCs
DATE '12 Proceedings of the Conference on Design, Automation and Test in Europe
Thermal analysis of periodic real-time systems with stochastic properties: an analytical approach
Proceedings of the 21st International conference on Real-Time Networks and Systems
Journal of Electronic Testing: Theory and Applications
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It has been the conventional assumption that, due to the superlinear dependence of leakage power consumption on temperature, and widely varying on-chip temperature profiles, accurate leakage estimation requires detailed knowledge of thermal profile. Leakage power depends on integrated circuit (IC) thermal profile and circuit design style. We show that linear models can be used to permit highly-accurate leakage estimation over the operating temperature ranges in real ICs. We then show that for typical IC packages and cooling structures, a given amount of heat introduced at any position in the active layer will have similar impact on the average temperature of the layer. These two observations allow us to prove that, for wide ranges of design styles and operating temperatures, extremely fast, coarse-grained thermal models, combined with linear leakage power consumption models, permit highly-accurate system-wide leakage power consumption estimation. The results of our proofs are further confirmed via comparisons with leakage estimation based on detailed, time-consuming thermal analysis techniques. Experimental results indicate that the proposed technique yields a 59,259×−1,790,000× speedup in leakage power estimation while maintaining accuracy.