Digital integrated circuits: a design perspective
Digital integrated circuits: a design perspective
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Real-time task scheduling under thermal constraints
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We consider a DVS-enabled single-processor firm real-time (FRT) system with Poisson arrival jobs having exponential execution times and generally distributed relative deadlines. The queue size of the system bounds the number of jobs which may be available therein. Further, the processor speed depends on the number of jobs in the system which varies because of the job arrivals, service completions, and deadline misses. Thus, the processor power consumption, including both the dynamic and leakage powers, depends on the stochastic nature of the system. More specifically, the instantaneous dynamic power consumption lonely depends on the number of jobs at that moment. However, the instantaneous leakage power consumption depends on both the number of jobs and the instantaneous processor temperature. In turn, the temperature is affected by both the dynamic and leakage power consumptions. Taking all the aforementioned inter-effects into account, this paper analytically models the timing, power and temperature behaviors of such a variable speed FRT system. The analysis is then employed to address the problem of the system average power (and thus, energy) minimization subject to guaranteeing some upper bound on the system loss probability. Simulation results are also put against the analytical ones to show the accuracy level of the proposed analytical method as well as the efficacy of the optimizations.