Wattch: a framework for architectural-level power analysis and optimizations
Proceedings of the 27th annual international symposium on Computer architecture
Predictive dynamic thermal management for multimedia applications
ICS '03 Proceedings of the 17th annual international conference on Supercomputing
Temperature-aware microarchitecture
Proceedings of the 30th annual international symposium on Computer architecture
Reducing power density through activity migration
Proceedings of the 2003 international symposium on Low power electronics and design
Dynamic Thermal Management for High-Performance Microprocessors
HPCA '01 Proceedings of the 7th International Symposium on High-Performance Computer Architecture
HPCA '02 Proceedings of the 8th International Symposium on High-Performance Computer Architecture
Single-ISA Heterogeneous Multi-Core Architectures: The Potential for Processor Power Reduction
Proceedings of the 36th annual IEEE/ACM International Symposium on Microarchitecture
Temperature-aware microarchitecture: Modeling and implementation
ACM Transactions on Architecture and Code Optimization (TACO)
Heat-and-run: leveraging SMT and CMP to manage power density through the operating system
ASPLOS XI Proceedings of the 11th international conference on Architectural support for programming languages and operating systems
Power-performance considerations of parallel computing on chip multiprocessors
ACM Transactions on Architecture and Code Optimization (TACO)
On Estimating Optimal Performance of CPU Dynamic Thermal Management
IEEE Computer Architecture Letters
Techniques for Multicore Thermal Management: Classification and New Exploration
Proceedings of the 33rd annual international symposium on Computer Architecture
An optimal analytical solution for processor speed control with thermal constraints
Proceedings of the 2006 international symposium on Low power electronics and design
Power efficiency for variation-tolerant multicore processors
Proceedings of the 2006 international symposium on Low power electronics and design
Dynamic thermal management for MPEG-2 decoding
Proceedings of the 2006 international symposium on Low power electronics and design
Mercury and freon: temperature emulation and management for server systems
Proceedings of the 12th international conference on Architectural support for programming languages and operating systems
Online power-performance adaptation of multithreaded programs using hardware event-based prediction
Proceedings of the 20th annual international conference on Supercomputing
Proceedings of the 39th Annual IEEE/ACM International Symposium on Microarchitecture
Hybrid multi-core architecture for boosting single-threaded performance
ACM SIGARCH Computer Architecture News
A study of thread migration in temperature-constrained multicores
ACM Transactions on Architecture and Code Optimization (TACO)
Efficient power modeling and software thermal sensing for runtime temperature monitoring
ACM Transactions on Design Automation of Electronic Systems (TODAES)
Temperature aware task scheduling in MPSoCs
Proceedings of the conference on Design, automation and test in Europe
Thousand core chips: a technology perspective
Proceedings of the 44th annual Design Automation Conference
Multi-core design automation challenges
Proceedings of the 44th annual Design Automation Conference
Thermal-aware scheduling for future chip multiprocessors
EURASIP Journal on Embedded Systems
Temperature-aware processor frequency assignment for MPSoCs using convex optimization
CODES+ISSS '07 Proceedings of the 5th IEEE/ACM international conference on Hardware/software codesign and system synthesis
Performance optimal processor throttling under thermal constraints
CASES '07 Proceedings of the 2007 international conference on Compilers, architecture, and synthesis for embedded systems
Studying Thermal Management for Graphics-Processor Architectures
ISPASS '05 Proceedings of the IEEE International Symposium on Performance Analysis of Systems and Software, 2005
Analysis of dynamic power management on multi-core processors
Proceedings of the 22nd annual international conference on Supercomputing
Variation-Aware Application Scheduling and Power Management for Chip Multiprocessors
ISCA '08 Proceedings of the 35th Annual International Symposium on Computer Architecture
Corollaries to Amdahl's Law for Energy
IEEE Computer Architecture Letters
Proceedings of the 2008 IEEE/ACM International Conference on Computer-Aided Design
Hotspot: acompact thermal modeling methodology for early-stage VLSI design
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Temperature and supply Voltage aware performance and power modeling at microarchitecture level
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Three-Dimensional Chip-Multiprocessor Run-Time Thermal Management
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Understanding the Thermal Implications of Multi-Core Architectures
IEEE Transactions on Parallel and Distributed Systems
Proceedings of the 20th International Conference on Real-Time and Network Systems
A multi-agent framework for thermal aware task migration in many-core systems
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Temperature-aware idle time distribution for leakage energy optimization
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Thermal analysis of periodic real-time systems with stochastic properties: an analytical approach
Proceedings of the 21st International conference on Real-Time Networks and Systems
Fast and accurate thermal modeling and simulation of manycore processors and workloads
Microelectronics Journal
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This paper describes a fast and accurate technique to predict the steady-state throughput and the corresponding power consumption of a homogeneous multicore processor for a given benchmark workload while accounting for speed reduction due to thermal constraints. The expressions contain several parameters of interest to a system designer, like the static and dynamic-power consumptions (for hottest block and for full chip), the vertical thermal resistance of the hottest block, the leakage sensitivity to temperature, the chip threshold temperature, the ambient temperature, etc. Their computational complexity is independent of the number of cores. These are incorporated in a system-level multicore power/thermal simulator that uses the PTScalar power model and the Hotspot thermal model. The analytical throughput and power predictions were within 1.7% of that predicted by the system-level simulator. However, the analytical technique takes less than 0.2 s for a given set of design parameters, making it well suited for early design-space exploration. In contrast, the numerical technique takes anywhere from a minute (for 4 cores) up to a few hours (for 25 cores).