Hotspot: acompact thermal modeling methodology for early-stage VLSI design

Authors:
Wei Huang;Shougata Ghosh;Siva Velusamy;Karthik Sankaranarayanan;Kevin Skadron;Mircea R. Stan
Affiliations:
the Charles L. Brown Department of Electrical and Computer Engineering, University of Virginia, Charlottesville, VA;Department of Electrical Engineering, Princeton University, Princeton, NJ and University of Virginia, Charlottesville, VA;Xilinx Inc., San Jose, CA and University of Virginia, Charlottesville, VA;Department of Computer Science, University of Virginia, Charlottesville, VA;Department of Computer Science, University of Virginia, Charlottesville, VA;the Charles L. Brown Department of Electrical and Computer Engineering, University of Virginia, Charlottesville, VA
Venue:
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Year:
2006

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Abstract

This paper presents HotSpot--a modeling methodology for developing compact thermal models based on the popular stacked-layer packaging scheme in modern very large-scale integration systems. In addition to modeling silicon and packaging layers, HotSpot includes a high-level on-chip interconnect self-heating power and thermal model such that the thermal impacts on interconnects can also be considered during early design stages. The HotSpot compact thermal modeling approach is especially well suited for preregister transfer level (RTL) and presynthesis thermal analysis and is able to provide detailed static and transient temperature information across the die and the package, as it is also computationally efficient.