Thermal via allocation for 3-D ICs considering temporally and spatially variant thermal power

Authors:
Hao Yu;Yiyu Shi;Lei He;Tanay Karnik
Affiliations:
Berkeley Design Automation, Santa Clara, CA;Department of Electrical Engineering, University of California, Los Angeles, CA;Department of Electrical Engineering, University of California, Los Angeles, CA;Intel Circuit Research Lab., Hillsboro, OR
Venue:
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Year:
2008

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Abstract

The existing 3-D thermal-via allocation methods are based on the steady-state thermal analysis and may lead to excessive number of thermal vias. This paper develops an accurate and efficient thermal-via allocation considering the temporally and spatially variant thermal-power. The transient temperature is calculated by macromodel with a one-time structured and parameterized model reduction, which also generates temperature sensitivity with respect to thermal-via density. The proposed thermal-via allocation minimizes the time-integral of temperature violation, and is solved by a sequential quadratic programming algorithm with use of sensitivities from the macromodel. Compared to the existing method using the steady-state thermal analysis, our method in experiments is 126 × faster to obtain temperature, and reduces the number of thermal vias by 2.04 × under the same temperature bound.