Reducing power in high-performance microprocessors
DAC '98 Proceedings of the 35th annual Design Automation Conference
On thermal effects in deep sub-micron VLSI interconnects
Proceedings of the 36th annual ACM/IEEE Design Automation Conference
Analysis for Complex Power Distribution Networks Considering Densely Populated Vias
ISQED '05 Proceedings of the 6th International Symposium on Quality of Electronic Design
Thermal via placement in 3D ICs
Proceedings of the 2005 international symposium on Physical design
The need for a full-chip and package thermal model for thermally optimized IC designs
ISLPED '05 Proceedings of the 2005 international symposium on Low power electronics and design
Demystifying 3D ICs: The Pros and Cons of Going Vertical
IEEE Design & Test
Physical Design for 3D System on Package
IEEE Design & Test
Fast thermal simulation for architecture level dynamic thermal management
ICCAD '05 Proceedings of the 2005 IEEE/ACM International conference on Computer-aided design
Thermal via planning for 3-D ICs
ICCAD '05 Proceedings of the 2005 IEEE/ACM International conference on Computer-aided design
ICCAD '05 Proceedings of the 2005 IEEE/ACM International conference on Computer-aided design
Proceedings of the 43rd annual Design Automation Conference
IBM Journal of Research and Development - POWER5 and packaging
PRIMA: passive reduced-order interconnect macromodeling algorithm
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Proceedings of the 2009 Asia and South Pacific Design Automation Conference
Allocating power ground vias in 3D ICs for simultaneous power and thermal integrity
ACM Transactions on Design Automation of Electronic Systems (TODAES)
Performance and thermal-aware Steiner routing for 3-D stacked ICs
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Complexity of 3-D floorplans by analysis of graph cuboidal dual hardness
ACM Transactions on Design Automation of Electronic Systems (TODAES)
Three-dimensional integrated circuits (3D IC) floorplan and power/ground network co-synthesis
Proceedings of the 2010 Asia and South Pacific Design Automation Conference
Power delivery design for 3-D ICs using different through-silicon via (TSV) technologies
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Thermal via allocation for 3-D ICs considering temporally and spatially variant thermal power
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Three-dimensional Integrated Circuits: Design, EDA, and Architecture
Foundations and Trends in Electronic Design Automation
Fast timing analysis of clock networks considering environmental uncertainty
Integration, the VLSI Journal
Thermal-aware P/G TSV planning for IR drop reduction in 3D ICs
Integration, the VLSI Journal
Benchmarking for research in power delivery networks of three-dimensional integrated circuits
Proceedings of the 2013 ACM international symposium on International symposium on physical design
A study of tapered 3-D TSVs for power and thermal integrity
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
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The existing work on via-stapling in 3D integrated circuits optimizes power and thermal integrity separately and uses steadystate thermal analysis. This paper presents the first in-depth study on simultaneous power and thermal integrity driven viastapling in 3D design. The transient temperature and supply voltage violations are calculated by a structured and parameterized model reduction, which also generates parameterized temperature and voltage violation sensitivities with respect to the via pattern and density. Using parameterized sensitivities, an efficient yet effective greedy optimization is presented to optimize power and thermal integrity simultaneously. Experiments with two active device layers show that compared to sequential power and thermal optimization using steady-state thermal analysis, sequential optimization using transient thermal analysis reduces non-signal vias by on average 11.5%, and simultaneous optimization using transient thermal analysis reduces non-signal vias by on average 34%. The via reduction would be higher for the 3D design with more device layers.