Run-time power control scheme using software feedback loop for low-power real-time application
ASP-DAC '00 Proceedings of the 2000 Asia and South Pacific Design Automation Conference
Full chip leakage estimation considering power supply and temperature variations
Proceedings of the 2003 international symposium on Low power electronics and design
Thermal via placement in 3D ICs
Proceedings of the 2005 international symposium on Physical design
3D module placement for congestion and power noise reduction
GLSVLSI '05 Proceedings of the 15th ACM Great Lakes symposium on VLSI
The need for a full-chip and package thermal model for thermally optimized IC designs
ISLPED '05 Proceedings of the 2005 international symposium on Low power electronics and design
A thermal-driven floorplanning algorithm for 3D ICs
Proceedings of the 2004 IEEE/ACM International conference on Computer-aided design
Thermal-driven multilevel routing for 3-D ICs
Proceedings of the 2005 Asia and South Pacific Design Automation Conference
Decoupling capacitor planning and sizing for noise and leakage reduction
Proceedings of the 2006 IEEE/ACM international conference on Computer-aided design
Simultaneous power and thermal integrity driven via stapling in 3D ICs
Proceedings of the 2006 IEEE/ACM international conference on Computer-aided design
Placement of 3D ICs with thermal and interlayer via considerations
Proceedings of the 44th annual Design Automation Conference
LEAF: A System Level Leakage-Aware Floorplanner for SoCs
ASP-DAC '07 Proceedings of the 2007 Asia and South Pacific Design Automation Conference
Proceedings of the 2007 IEEE/ACM international conference on Computer-aided design
Thermal-Aware IR Drop Analysis in Large Power Grid
ISQED '08 Proceedings of the 9th international symposium on Quality Electronic Design
Congestion-aware power grid optimization for 3D circuits using MIM and CMOS decoupling capacitors
Proceedings of the 2009 Asia and South Pacific Design Automation Conference
Addressing thermal and power delivery bottlenecks in 3D circuits
Proceedings of the 2009 Asia and South Pacific Design Automation Conference
Three-dimensional integrated circuits (3D IC) floorplan and power/ground network co-synthesis
Proceedings of the 2010 Asia and South Pacific Design Automation Conference
Multi-objective module placement for 3-d system-on-package
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
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With the leakage-thermal dependency, the increasing on-chip temperature in 3D designs has serious impact on IR drop due to the increased wire resistance and increased leakage current. Therefore, it is necessary to consider Power/Ground network design with thermal effects in 3D designs. Though Power/Ground (P/G) TSV can help to relieve the IR drop violation by vertically connecting on-chip P/G networks on different layers, most previous work restricts the uniform P/G grids so that the potential of P/G TSV planning has not been fully explored. In this paper, we present an efficient thermal-aware P/G TSV planning algorithm based on a sensitivity model with temperature-dependent leakage current considered. Non-uniform P/G grid topology is explored to optimize the P/G network by allowing short wires to connect the P/G TSVs to P/G grids. Both the theoretical analysis and experimental results show the efficiency of our approach. Results show that neglecting thermal impacts on power delivery can underestimate IR drop by about 11%. To relieve the severe IR drop violation, 51.8% more P/G TSVs are needed than the cases without thermal impacts considered. Results also show that our P/G TSV planning based on the sensitivity model can reduce max IR drop by 42.3% and reduce the number of violated nodes by 82.4%.