Proceedings of the 2007 IEEE/ACM international conference on Computer-aided design
Statistical power profile correlation for realistic thermal estimation
Proceedings of the 2008 Asia and South Pacific Design Automation Conference
TRAM: a tool for temperature and reliability aware memory design
Proceedings of the Conference on Design, Automation and Test in Europe
Floorplanning for low power IC design considering temperature variations
Microelectronics Journal
Thermal-aware P/G TSV planning for IR drop reduction in 3D ICs
Integration, the VLSI Journal
| Hi-index | 0.00 |
Process scaling and higher leakage power have resulted in increased power densities and elevated die temperatures. Due to the interdependence of temperature and leakage power, we observe that the floorplan has an impact on both the temperatures and the leakage of the IP-blocks in a system on chip (SoC). Hence, in this paper we propose a novel system level leakage aware floorplanner (LEAF) which optimizes floorplans for temperature-aware leakage power along with the traditional metrics of area and wire length. Our floorplanner takes a SoC netlist and the dynamic power profile of functional blocks to determine a placement while optimizing for temperature dependent leakage power, area, and wire length. To demonstrate the effectiveness of LEAF, we implemented our methodology on ten industrial SoC designs from Freescale Semiconductor Inc. and evaluated the trade-off between leakage power and area. We observed up to 190% difference in the leakage power between leakage-unaware and leakage aware floorplanning.