An O-tree representation of non-slicing floorplan and its applications
Proceedings of the 36th annual ACM/IEEE Design Automation Conference
A new algorithm for floorplan design
DAC '86 Proceedings of the 23rd ACM/IEEE Design Automation Conference
Wattch: a framework for architectural-level power analysis and optimizations
Proceedings of the 27th annual international symposium on Computer architecture
An Introduction to VLSI Physical Design
An Introduction to VLSI Physical Design
Parameter variations and impact on circuits and microarchitecture
Proceedings of the 40th annual Design Automation Conference
Full chip leakage estimation considering power supply and temperature variations
Proceedings of the 2003 international symposium on Low power electronics and design
Gate leakage reduction for scaled devices using transistor stacking
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Hybrid Architectural Dynamic Thermal Management
Proceedings of the conference on Design, automation and test in Europe - Volume 1
Thermal-Aware Floorplanning Using Genetic Algorithms
ISQED '05 Proceedings of the 6th International Symposium on Quality of Electronic Design
Microarchitecture-aware floorplanning using a statistical design of experiments approach
Proceedings of the 42nd annual Design Automation Conference
Joint exploration of architectural and physical design spaces with thermal consideration
ISLPED '05 Proceedings of the 2005 international symposium on Low power electronics and design
A thermal-driven floorplanning algorithm for 3D ICs
Proceedings of the 2004 IEEE/ACM International conference on Computer-aided design
Microarchitectural floorplanning under performance and thermal tradeoff
Proceedings of the conference on Design, automation and test in Europe: Proceedings
A revisit to floorplan optimization by Lagrangian relaxation
Proceedings of the 2006 IEEE/ACM international conference on Computer-aided design
Microarchitecture floorplanning for sub-threshold leakage reduction
Proceedings of the conference on Design, automation and test in Europe
LEAF: A System Level Leakage-Aware Floorplanner for SoCs
ASP-DAC '07 Proceedings of the 2007 Asia and South Pacific Design Automation Conference
Thermal-aware floorplanning for task migration enabled active sub-threshold leakage reduction
Proceedings of the 2008 IEEE/ACM International Conference on Computer-Aided Design
Thermal optimization in multi-granularity multi-core floorplanning
Proceedings of the 2009 Asia and South Pacific Design Automation Conference
Fixed-outline floorplanning: enabling hierarchical design
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Modeling and analysis of nonuniform substrate temperature effects on global ULSI interconnects
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
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Non-uniformity in thermal profiles of integrated circuits (ICs) is an issue that threatens their performance and reliability. This paper investigates the correlation between the total power consumption and the temperature variations across a chip. As a result, floorplanning guidelines are proposed that uses the correlation to efficiently optimize the chip's total power and takes into account the thermal uniformity. It is demonstrated that optimizing a floorplan to minimize either the leakage or the peak temperature can lead to a significant increase in the total power consumption. In this paper, the experimental results show that lowering the temperature variations across a chip not only addresses performance degradation and reliability concerns, but also significantly contributes to chip power reduction. In addition, it is found that although uniformity in the thermal profile can be very effective in lowering the total power consumption, the most uniform temperature distribution does not necessarily correspond to the highest power savings. Consequently, for some applications, a 2% deviation from the minimum total power is traded for up to a 25% increase in thermal uniformity. The presented method is implemented for an Alpha 21264 processor running Spec 2000 benchmarks.