Gate leakage reduction for scaled devices using transistor stacking

Authors:
Saibal Mukhopadhyay;Cassondra Neau;Riza Tamer Cakici;Amit Agarwal;Chris H. Kim;Kaushik Roy
Affiliations:
School of Electrical and Computer Engineering, Purdue University, West Lafayette, IN;School of Electrical and Computer Engineering, Purdue University, West Lafayette, IN;School of Electrical and Computer Engineering, Purdue University, West Lafayette, IN;School of Electrical and Computer Engineering, Purdue University, West Lafayette, IN;School of Electrical and Computer Engineering, Purdue University, West Lafayette, IN;School of Electrical and Computer Engineering, Purdue University, West Lafayette, IN
Venue:
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Year:
2003

Citing 4
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Abstract

In this paper, the effect of gate tunneling current in ultra-thin gate oxide MOS devices of effective length (Leff) of 25 nm ( oxide thickness = 1.1 nm), 50 nm ( oxide thickness = 1.5 nm) and 90 nm( oxide thickness = 2.5 nm) is studied using device simulation. Overall leakage in a stack of transistors is modeled and the opportunities for leakage reduction in the standby mode of operation are explored for scaled technologies. It is shown that, as the contribution of gate leakage relative to the total leakage increases with technology scaling, traditional techniques become ineffective in reducing overall leakage current in a circuit. A novel technique of input vector selection based on the relative contributions of gate and subthreshold leakage to the overall leakage is proposed for reducing total leakage in a circuit. This technique results in 44% savings in total leakage in 50-nm devices compared to the conventional stacking technique.