ISLPED '98 Proceedings of the 1998 international symposium on Low power electronics and design
Design and optimization of dual-threshold circuits for low-voltage low-power applications
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Intrinsic leakage in deep submicron CMOS ICs—measurement-based test solutions
IEEE Transactions on Very Large Scale Integration (VLSI) Systems - Special issue on system-level interconnect prediction
A novel probabilistic approach for IC diagnosis based on differential quiescent current signatures
VTS '97 Proceedings of the 15th IEEE VLSI Test Symposium
Current Ratios: A Self-Scaling Technique for Production IDDQ Testing
ITC '00 Proceedings of the 2000 IEEE International Test Conference
Multiple-Parameter CMOS IC Testing with Increased Sensitivity for IDDQ
ITC '00 Proceedings of the 2000 IEEE International Test Conference
Clustering Based Techniques for IDDQ Testing
ITC '99 Proceedings of the 1999 IEEE International Test Conference
IDDQ Test: Will It Survive the DSM Challenge?
IEEE Design & Test
Neighborhood Selection for IDDQ Outlier Screening at Wafer Sort
IEEE Design & Test
Gate leakage reduction for scaled devices using transistor stacking
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
IDDX-based test methods: A survey
ACM Transactions on Design Automation of Electronic Systems (TODAES)
ISQED '05 Proceedings of the 6th International Symposium on Quality of Electronic Design
Low-power design techniques for scaled technologies
Integration, the VLSI Journal - Special issue: Low-power design techniques
Low-power design techniques for scaled technologies
Integration, the VLSI Journal - Special issue: Low-power design techniques
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The use of low-threshold devices in scaled low-voltage CMOS circuits leads to increased intrinsic leakage current. As a result, IDDQ testing requires different techniques to remain effective.