Technology and design challenges for low power and high performance
ISLPED '99 Proceedings of the 1999 international symposium on Low power electronics and design
ISLPED '99 Proceedings of the 1999 international symposium on Low power electronics and design
IEEE Design & Test
IDDQ Test: Sensitivity Analysis of Scaling
Proceedings of the IEEE International Test Conference on Test and Design Validity
IDDQ Characterization in Submicron CMOS
Proceedings of the IEEE International Test Conference
Intrinsic Leakage in Low-Power Deep Submicron CMOS ICs
Proceedings of the IEEE International Test Conference
So What Is an Optimal Test Mix? A Discussion of the SEMATECH Methods Experiment
Proceedings of the IEEE International Test Conference
Current Signatures: Application
Proceedings of the IEEE International Test Conference
High volume microprocessor test escapes, an analysis of defects our tests are missing
ITC '98 Proceedings of the 1998 IEEE International Test Conference
Defect detection with transient current testing and its potential for deep sub-micron CMOS ICs
ITC '98 Proceedings of the 1998 IEEE International Test Conference
Deep Sub-Micron IDDQ Testing: Issues and Solutions
EDTC '97 Proceedings of the 1997 European conference on Design and Test
An Histogram Based Procedure for Current Testing of Active Defects
ITC '99 Proceedings of the 1999 IEEE International Test Conference
Current Ratios: A Self-Scaling Technique for Production IDDQ Testing
ITC '99 Proceedings of the 1999 IEEE International Test Conference
IDDQ Testing in Deep Submicron Integrated Circuits
ITC '99 Proceedings of the 1999 IEEE International Test Conference
Transient Current Testing of 0.25 µm CMOS Devices
ITC '99 Proceedings of the 1999 IEEE International Test Conference
Current-Based Testing for Deep-Submicron VLSIs
IEEE Design & Test
IDDQ Testing for Deep-Submicron ICs: Challenges and Solutions
IEEE Design & Test
IDDQ Test: Will It Survive the DSM Challenge?
IEEE Design & Test
The Future of Delta IDDQ Testing
ITC '01 Proceedings of the 2001 IEEE International Test Conference
Built-in Current Sensor for "I{DDQ} Testing of Deep Submicron Digital CMOS ICs
VTS '04 Proceedings of the 22nd IEEE VLSI Test Symposium
IDDX-based test methods: A survey
ACM Transactions on Design Automation of Electronic Systems (TODAES)
IDDQ data analysis using neighbor current ratios
Journal of Systems Architecture: the EUROMICRO Journal - Special issue: Desing and test of systems on a chip
Test Consideration for Nanometer-Scale CMOS Circuits
IEEE Design & Test
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Technology scaling challenges the effectiveness of currentbasedtest techniques such as IDDQ. Furthermore, existingleakage reduction techniques are not as effective inaggressively scaled technologies. We exploited intrinsicdependencies of transistor and circuit leakage on clockfrequency, temperature, and reverse body bias (RBB) todiscriminate fast ICs from defective ones. Transistor andcircuit parameters were measured and correlated todemonstrate leakage-based testing solutions with improvedsensitivity. We used a test IC with available body terminalsfor our experimental measurements. Our data suggestadopting a sensitive multiple-parameter test solution. Forhigh performance IC applications, we propose a new testtechnique, IDDQ versus FMAX (maximum operatingfrequency), in conjunction with using temperature (orRBB) to improve the defect detection sensitivity. For costsensitive applications, IDDQ versus temperature test can bedeployed. Our data show that temperature (cooling from110 oC to room) improved sensitivity of IDDQ versus FMAXtwo-parameter test by more than an order of magnitude(13.8X). The sensitivity can also be tuned by properselection of a temperature range to match a required DPMlevel.