IEEE Spectrum
Algorithms for current monitor based diagnosis of bridging and leakage faults
DAC '92 Proceedings of the 29th ACM/IEEE Design Automation Conference
Journal of Electronic Testing: Theory and Applications - Special issue on IDDQ testing of VLSI circuits
Diagnosis of leakage faults with IDDQ
Journal of Electronic Testing: Theory and Applications - Special issue on IDDQ testing of VLSI circuits
Identifying defects in deep-submicron CMOS ICs
IEEE Spectrum
Test Generation for Current Testing (CMOS ICs)
IEEE Design & Test
IC Failure Analysis: Magic, Mystery, and Science
IEEE Design & Test
Increasing Current Testing Resolution
DFT '98 Proceedings of the 13th International Symposium on Defect and Fault-Tolerance in VLSI Systems
IDDQ Test: Sensitivity Analysis of Scaling
Proceedings of the IEEE International Test Conference on Test and Design Validity
So What Is an Optimal Test Mix? A Discussion of the SEMATECH Methods Experiment
Proceedings of the IEEE International Test Conference
Estimation of defect-free IDDQ in submicron circuits using switch level simulation
ITC '98 Proceedings of the 1998 IEEE International Test Conference
High volume microprocessor test escapes, an analysis of defects our tests are missing
ITC '98 Proceedings of the 1998 IEEE International Test Conference
Diagnosis method based on /spl Delta/Iddq probabilistic signatures: experimental results
ITC '98 Proceedings of the 1998 IEEE International Test Conference
A novel built-in current sensor for I/sub DDQ/ testing of deep submicron CMOS ICs
VTS '96 Proceedings of the 14th IEEE VLSI Test Symposium
Current signatures [VLSI circuit testing]
VTS '96 Proceedings of the 14th IEEE VLSI Test Symposium
On estimating bounds of the quiescent current for I/sub DDQ/ testin
VTS '96 Proceedings of the 14th IEEE VLSI Test Symposium
VTS '97 Proceedings of the 15th IEEE VLSI Test Symposium
A novel probabilistic approach for IC diagnosis based on differential quiescent current signatures
VTS '97 Proceedings of the 15th IEEE VLSI Test Symposium
On the Comparison of IDDQ and IDDQ Testing
VTS '99 Proceedings of the 1999 17TH IEEE VLSI Test Symposium
Current Signatures for Production Testing
IDDQ '96 Proceedings of the 1996 IEEE International Workshop on IDDQ Testing (IDDQ '96)
A Simulation-Based Method for Estimating Defect-Free IDDQ
IDDQ '97 Proceedings of the 1997 IEEE International Workshop on IDDQ Testing (IDDQ '97)
Detection and location of faults and defects using digital signal processing
VTS '95 Proceedings of the 13th IEEE VLSI Test Symposium
Current Ratios: A Self-Scaling Technique for Production IDDQ Testing
ITC '99 Proceedings of the 1999 IEEE International Test Conference
Diagnosis Method Using ΔIDDQ Probabilistic Signatures: Theory and Results
Journal of Electronic Testing: Theory and Applications
Current Testing Procedure for Deep Submicron Devices
Journal of Electronic Testing: Theory and Applications
Studies of the SEMATECH IDDq test data
Journal of Systems Architecture: the EUROMICRO Journal - Defect and fault tolerance in VLSI Systems
Deep Submicron CMOS Current IC Testing: Is There a Future?
IEEE Design & Test
Current-Based Testing for Deep-Submicron VLSIs
IEEE Design & Test
IDDQ Test: Will It Survive the DSM Challenge?
IEEE Design & Test
Neighborhood Selection for IDDQ Outlier Screening at Wafer Sort
IEEE Design & Test
Replacing IDDQ Testing: With Variance Reduction
Journal of Electronic Testing: Theory and Applications
Leakage Current in Sub-Quarter Micron MOSFET: A Perspective on Stressed Delta IDDQ Testing
Journal of Electronic Testing: Theory and Applications
Current Testing Procedure for Deep Submicron Devices
ETW '00 Proceedings of the IEEE European Test Workshop
Immediate Neighbor Difference IDDQ Test (INDIT) for Outlier Identification
VLSID '03 Proceedings of the 16th International Conference on VLSI Design
On the Comparison of IDDQ and IDDQ Testing
VTS '99 Proceedings of the 1999 17TH IEEE VLSI Test Symposium
Current Ratios: A Self-Scaling Technique for Production IDDQ Testing
ITC '00 Proceedings of the 2000 IEEE International Test Conference
Precise Test Generation for Resistive Bridging Faults of CMOS Combinational Circuits
ITC '00 Proceedings of the 2000 IEEE International Test Conference
Multiple-Parameter CMOS IC Testing with Increased Sensitivity for IDDQ
ITC '00 Proceedings of the 2000 IEEE International Test Conference
Improving Delta-IDDQ-based test methods
ITC '00 Proceedings of the 2000 IEEE International Test Conference
VARIANCE REDUCTION USING WAFER PATTERNS in IddQ DATA
ITC '00 Proceedings of the 2000 IEEE International Test Conference
Increasing the IDDQ Test Resolution Using Current Prediction
ITC '00 Proceedings of the 2000 IEEE International Test Conference
The Future of Delta IDDQ Testing
ITC '01 Proceedings of the 2001 IEEE International Test Conference
NEIGHBOR SELECTION FOR VARIANCE REDUCTION IN IDDQ and OTHER PARAMETRIC DATA
ITC '01 Proceedings of the 2001 IEEE International Test Conference
A Practical Built-In Current Sensor for IDDQ Testing
ITC '01 Proceedings of the 2001 IEEE International Test Conference
Current Ratios: A Self-Scaling Technique for Production IDDQ Testing
ITC '99 Proceedings of the 1999 IEEE International Test Conference
IDDQ Testing in Deep Submicron Integrated Circuits
ITC '99 Proceedings of the 1999 IEEE International Test Conference
Journal of Electronic Testing: Theory and Applications
Multiple-parameter CMOS IC testing with increased sensitivity for IDDQ
IEEE Transactions on Very Large Scale Integration (VLSI) Systems - Special section on low power
On New Current Signatures and Adaptive Test Technique Combination
VTS '04 Proceedings of the 22nd IEEE VLSI Test Symposium
On Comparison of NCR Effectiveness with a Reduced I{DDQ} Vector Set
VTS '04 Proceedings of the 22nd IEEE VLSI Test Symposium
IDDX-based test methods: A survey
ACM Transactions on Design Automation of Electronic Systems (TODAES)
IDDQ data analysis using neighbor current ratios
Journal of Systems Architecture: the EUROMICRO Journal - Special issue: Desing and test of systems on a chip
| Hi-index | 0.00 |
The purpose of this paper is to propose a newhistogram-based differential current testing procedure ofactive defects. This procedure contains three steps: Pre-analysis,Failure Analysis, and Production Testing. Themain objectives of the Pre-analysis are to provideinformation on the most frequent active current defectsand to help setting the limits between faulty and fault-freedevices; these limits are then investigated during theFailure Analysis step in order to set the threshold betweenfaulty and fault-free ICs. During the Production Testingstep, this threshold is compared to the highest peak valueappearing in a histogram built for each tested IC. Someselected results are presented, which confirm the testquality gain increase by using differential IDDQ instead ofIDDQ itself as well as the additional reduction of bad testdecision that can be obtained by a wise selection of testvectors reducing the vector-to-vector current variations.