Leakage control with efficient use of transistor stacks in single threshold CMOS
Proceedings of the 36th annual ACM/IEEE Design Automation Conference
Leakage control with efficient use of transistor stacks in single threshold CMOS
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
LEAP: An Accurate Defect-Free IDDQ Estimator
Journal of Electronic Testing: Theory and Applications
Estimation of defect-free IDDQ in submicron circuits using switch level simulation
ITC '98 Proceedings of the 1998 IEEE International Test Conference
LEAP: An Accurate Defect-Free IDDQ Estimator
ETW '00 Proceedings of the IEEE European Test Workshop
On the Comparison of IDDQ and IDDQ Testing
VTS '99 Proceedings of the 1999 17TH IEEE VLSI Test Symposium
An Histogram Based Procedure for Current Testing of Active Defects
ITC '99 Proceedings of the 1999 IEEE International Test Conference
| Hi-index | 0.00 |
This paper presents a switch-level simulation-based method for estimating quiescent current values. The simulator identifies transistors that are in the proper state to experience leakage mechanisms. This information is combined with data about both the size of these transistors and various process parameters in order to calculate the actual IDDQ value. SPICE simulation results are also presented on a variety of circuits to both calibrate the simulator, and to demonstrate state, time and sequence dependencies of circuits.