ISLPED '98 Proceedings of the 1998 international symposium on Low power electronics and design
IDDQ Test: Sensitivity Analysis of Scaling
Proceedings of the IEEE International Test Conference on Test and Design Validity
Burn-in Elimination of a High Volume Microprocessor Using IDDQ
Proceedings of the IEEE International Test Conference on Test and Design Validity
Current Signatures: Application
Proceedings of the IEEE International Test Conference
Estimation of defect-free IDDQ in submicron circuits using switch level simulation
ITC '98 Proceedings of the 1998 IEEE International Test Conference
Iddq Testing for High Performance CMOS - The Next Ten Years
EDTC '96 Proceedings of the 1996 European conference on Design and Test
On estimating bounds of the quiescent current for I/sub DDQ/ testin
VTS '96 Proceedings of the 14th IEEE VLSI Test Symposium
A Simulation-Based Method for Estimating Defect-Free IDDQ
IDDQ '97 Proceedings of the 1997 IEEE International Workshop on IDDQ Testing (IDDQ '97)
Current Ratios: A Self-Scaling Technique for Production IDDQ Testing
ITC '99 Proceedings of the 1999 IEEE International Test Conference
Defect classes - an overdue paradigm for CMOS IC testing
ITC'94 Proceedings of the 1994 international conference on Test
Models and algorithms for bounds on leakage in CMOS circuits
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
The Future of Delta IDDQ Testing
ITC '01 Proceedings of the 2001 IEEE International Test Conference
IDDX-based test methods: A survey
ACM Transactions on Design Automation of Electronic Systems (TODAES)
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The quiescent current (IDDQ) consumed by a CMOS IC is a good indicator of the presence of a large class of defects. However, the effectiveness of IDDQ testing requires appropriate discriminability of defective and defect-free currents, and hence it becomes necessary to estimate the currents involved in order to design the IDDQ test. In this work, we present a method to estimate accurately the non-defective IDDQ consumption based on a hierarchical approach at electrical (cell) and logic (circuit) levels. This accurate estimator is used in conjunction with an ATPG (Automatic Test Pattern Generation) to obtain vectors having low/high defect-free IDDQ currents.