Defect classes - an overdue paradigm for CMOS IC testing

Authors:
Charles F. Hawkins;Jerry M. Soden;Alan W. Righter;F. Joel Ferguson
Affiliations:
Electrical and Computer Eng. Dept., University of New Mexico, Albuquerque, New Mexico;Failure Analysis, MCM Applications, Sandia National Labs, Albuquerque, New Mexico;Failure Analysis, MCM Applications, Sandia National Labs, Albuquerque, New Mexico;Computer Engineering Dept., University of California - Santa Cruz, Santa Cruz, California
Venue:
ITC'94 Proceedings of the 1994 international conference on Test
Year:
1994

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Abstract

The IC test industry has struggled for more than 30 years to establish a test approach that would guarantee a low defect level to the customer. We propose a comprehensive strategy for testing CMOS ICs that uses defect classes based on measured defect electrical properties. Defect classes differ from traditional fault models. Our defect class approach requires that the test strategy match the defect electrical properties, while fault models require that IC defects match the fault definition. We use data from Sandia Labs failure analysis and test facilities and from public literature [1-60]. We describe test pattern requirements for each defect class and propose a test paradigm.