IDDQ testing as a component of a test suite: the need for several fault coverage metrics
Journal of Electronic Testing: Theory and Applications - Special issue on IDDQ testing of VLSI circuits
Accurate and efficient fault simulation of realistic CMOS network breaks
DAC '95 Proceedings of the 32nd annual ACM/IEEE Design Automation Conference
Introduction to IDDQ testing
Using Target Faults To Detect Non-Tartget Defects
Proceedings of the IEEE International Test Conference on Test and Design Validity
Application and Analysis of IDDQ Diagnostic Software
Proceedings of the IEEE International Test Conference
Failure analysis of timing and IDDq-only failures from the SEMATECH test methods experiment
ITC '98 Proceedings of the 1998 IEEE International Test Conference
A Comparison of Defect Models for Fault Location with IDDQ Measurements
Proceedings of the IEEE International Test Conference on Discover the New World of Test and Design
A General Purpose IDDQ Measurement Circuit
Proceedings of the IEEE International Test Conference on Designing, Testing, and Diagnostics - Join Them
A Comparison of Stuck-At Fault Coverage and IDDQ Testing on Defect Levels
Proceedings of the IEEE International Test Conference on Designing, Testing, and Diagnostics - Join Them
Inductive Fault Analysis of MOS Integrated Circuits
IEEE Design & Test
Defect classes - an overdue paradigm for CMOS IC testing
ITC'94 Proceedings of the 1994 international conference on Test
Simulation results of an efficient defect analysis procedure
ITC'94 Proceedings of the 1994 international conference on Test
Fault models and test generation for IDDQ testing: embedded tutorial
ASP-DAC '00 Proceedings of the 2000 Asia and South Pacific Design Automation Conference
IDDX-based test methods: A survey
ACM Transactions on Design Automation of Electronic Systems (TODAES)
CδIDDQ: improving current-based testing and diagnosis through modified test pattern generation
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
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Since its inception, the pseudo-stuck-at fault model has demonstrated its usefulness in generating IDDQ patterns, calculating coverage, and diagnosing defects. However, the model's definition has lacked rigor, which has resulted in multiple, incompatible, interpretations. This paper provides a complete definition for the model and demonstrates how variations will cause a loss of defect coverage. The covering relationship between the pseudo-stuck-at (PSA) model and leakage faults is proven for all combinational CMOS cells. This relationship is extended to show the effect that undetectable PSA faults have on leakage fault coverage. It is shown how to apply the model to sequential cells such as flip-flops and latches. The PSA model is also extended to cover both short and open faults in chip interconnect. A weighting function is introduced to tie the coverage more closely to process defect statistics. Finally, experimental results are given to show the effectiveness of the model on actual ASICs.