Realistic fault modeling for VLSI testing
DAC '87 Proceedings of the 24th ACM/IEEE Design Automation Conference
The Effect of Different Test Sets on Quality Level Prediction: When is 80% better than 90%?
Proceedings of the IEEE International Test Conference on Test: Faster, Better, Sooner
Physical DFT for High Coverage of Realistic Faults
Proceedings of the IEEE International Test Conference on Discover the New World of Test and Design
Very-Low-Voltage Testing for Weak CMOS Logic ICs
Proceedings of the IEEE International Test Conference on Designing, Testing, and Diagnostics - Join Them
A strategy for testability enhancement at layout level
EURO-DAC '90 Proceedings of the conference on European design automation
The effectiveness of different test sets for PLAs
EURO-DAC '90 Proceedings of the conference on European design automation
Physical Versus Logical Fault Models MOS LSI Circuits: Impact on Their Testability
IEEE Transactions on Computers
Modeling of integrated circuit defect sensitivities
IBM Journal of Research and Development
Extending the Pseudo-Stuck-At Fault Model to Provide Complete IDDQ Coverage
VTS '99 Proceedings of the 1999 17TH IEEE VLSI Test Symposium
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For obtaining a zero defect level, a high fault coverage with respect to the stuck-at fault model is often not sufficient as there are many defects that show a more complex behavior. In this paper, a method is presented for computing the occurrence probabilities of certain defects and the realistic fault coverage for test sets. The method is highly efficient as a pre-processing step is used for partitioning the layout and extracting the defects ranked in the order of their occurrence probabilities. The method was applied to a public domain library where defects causing a complex faulty behavior are possible. The occurrence probability of these faults was computed, and the defect coverage for different test sets was determined.