Evaluation of On-Chip Static Interconnection Networks
IEEE Transactions on Computers
Cache RAM inductive fault analysis with fab defect modeling
ITC '98 Proceedings of the 1998 IEEE International Test Conference
Accurate yield estimation of circuits with redundancy
DFT '95 Proceedings of the IEEE International Workshop on Defect and Fault Tolerance in VLSI Systems
Yield projection from defect monitors: the influence of gross defects [BiCMOS process]
DFT '95 Proceedings of the IEEE International Workshop on Defect and Fault Tolerance in VLSI Systems
Critical area extraction of extra material soft faults
DFT '95 Proceedings of the IEEE International Workshop on Defect and Fault Tolerance in VLSI Systems
The effect of spot defects on the parametric yield of long interconnection lines
DFT '95 Proceedings of the IEEE International Workshop on Defect and Fault Tolerance in VLSI Systems
AFFCCA: a tool for critical area analysis with circular defects and lithography deformed layout
DFT '95 Proceedings of the IEEE International Workshop on Defect and Fault Tolerance in VLSI Systems
Approximation of critical area of ICs with simple parameters extracted from the layout
DFT '95 Proceedings of the IEEE International Workshop on Defect and Fault Tolerance in VLSI Systems
Hierarchical extraction of critical area for shorts in very large ICs
DFT '95 Proceedings of the IEEE International Workshop on Defect and Fault Tolerance in VLSI Systems
Hierarchical critical area extraction with the EYE tool
DFT '95 Proceedings of the IEEE International Workshop on Defect and Fault Tolerance in VLSI Systems
Testability-oriented channel routing
VLSID '95 Proceedings of the 8th International Conference on VLSI Design
A framework for early and systematic evaluation of design rules
Proceedings of the 2009 International Conference on Computer-Aided Design
Residual charge on the faulty floating gate MOS transistor
ITC'94 Proceedings of the 1994 international conference on Test
Back annotation of physical defects into gate-level, realistic faults in digital ICs
ITC'94 Proceedings of the 1994 international conference on Test
Simulation results of an efficient defect analysis procedure
ITC'94 Proceedings of the 1994 international conference on Test
A BIST design of structured arrays with fault-tolerant layout
ITC'88 Proceedings of the 1988 international conference on Test: new frontiers in testing
Regular fabric for regular FPGA (abstract only)
Proceedings of the 19th ACM/SIGDA international symposium on Field programmable gate arrays
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Until now only cursory descriptions of mathematical models for defect sensitivities of integrated circuit chips have been given in the yield literature. This paper treats the fundamentals of the defect models that have been used successfully at IBM for a period of more than fifteen years. The effects of very small defects are discussed first. The case of photolithographic defects, which are of the same dimensions as the integrated circuit device and interconnection patterns, is dealt with in the remainder of the paper. The relationships between these models and test sites are described. Data from measurements of defect sizes are discussed.