Automatic layout of domain-specific reconfigurable subsystems for system-on-a-chip
FPGA '02 Proceedings of the 2002 ACM/SIGDA tenth international symposium on Field-programmable gate arrays
Automatic transistor and physical design of FPGA tiles from an architectural specification
FPGA '03 Proceedings of the 2003 ACM/SIGDA eleventh international symposium on Field programmable gate arrays
Optimal layout of CMOS functional arrays
DAC '79 Proceedings of the 16th Design Automation Conference
Design, layout and verification of an FPGA using automated tools
Proceedings of the 2005 ACM/SIGDA 13th international symposium on Field-programmable gate arrays
Analysis and mitigation of variability in subthreshold design
ISLPED '05 Proceedings of the 2005 international symposium on Low power electronics and design
Modeling of integrated circuit defect sensitivities
IBM Journal of Research and Development
A framework for early and systematic evaluation of design rules
Proceedings of the 2009 International Conference on Computer-Aided Design
On Electrical Modeling of Imperfect Diffusion Patterning
VLSID '10 Proceedings of the 2010 23rd International Conference on VLSI Design
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
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In the sub-wavelength regime, design for manufacturability (DFM) becomes increasingly important for field programmable gate arrays (FPGAs). In this paper, we report an automated tile generation flow targeting micro-regular fabric, this flow automatically generate the basic FPGA tile building block in a standard cell format and then form the whole tile with the help of commercial placing and routing tools. Using a publicly accessible, well-documented academic FPGA as case study, we found that comparing to the tile generators previously reported, our generated micro-regular tile incurs less than 10% area overhead, which could be potentially recovered by process window optimization thanks to its superior printability. In addition, we demonstrate that on 45nm technology, the generated FPGA tile reduces lithography induced process variation by 33%; and reduce probability of failure by 21.2%. If further overhead of 10% area can be recovered by enhanced resolution, we can achieve the variation reduction of 93.8% and reduce probability of failure by 16.2%.