Cost of silicon viewed from VLSI design perspective
DAC '94 Proceedings of the 31st annual Design Automation Conference
Layout impact of resolution enhancement techniques: impediment or opportunity?
Proceedings of the 2003 international symposium on Physical design
Design methodology for IC manufacturability based on regular logic-bricks
Proceedings of the 42nd annual Design Automation Conference
Backend CAD flows for "restrictive design rules"
Proceedings of the 2004 IEEE/ACM International conference on Computer-aided design
Exact combinatorial optimization methods for physical design of regular logic bricks
Proceedings of the 44th annual Design Automation Conference
OPC-free and minimally irregular IC design style
Proceedings of the 44th annual Design Automation Conference
Regular fabric for regular FPGA (abstract only)
Proceedings of the 19th ACM/SIGDA international symposium on Field programmable gate arrays
Transistor sizing in lithography-aware regular fabrics
Proceedings of the 24th symposium on Integrated circuits and systems design
Area impact analysis of via-configurable regular fabric for digital integrated circuit design
Proceedings of the 24th symposium on Integrated circuits and systems design
Circuit design challenges at the 14nm technology node
Proceedings of the 48th Design Automation Conference
Standard cell routing via boolean satisfiability
Proceedings of the 49th Annual Design Automation Conference
Standard cell like via-configurable logic blocks for structured ASIC in an industrial design flow
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Nonrandom device mismatch considerations in Nanoscale SRAM
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Fixed origin corner square inspection layout regularity metric
DATE '12 Proceedings of the Conference on Design, Automation and Test in Europe
Design and analysis of via-configurable routing fabrics for structured ASICs
DATE '12 Proceedings of the Conference on Design, Automation and Test in Europe
Systematic and random variability analysis of two different 6T-SRAM layout topologies
Microelectronics Journal
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The financial backbone of the semiconductor industry is based on doubling the functional density of integrated circuits every two years at fixed wafer costs and die yields. The increasing demands for 'computational' rather than 'physical' lithography to achieve the aggressive density targets, along with the complex device-engineering solutions needed to maintain the power density objectives, have caused a rapid escalation in systematic yield limiters that threaten scaling. Specifically, the traditional contract between design and manufacturing based solely on design rules is no longer sufficient to guarantee functional silicon and instead requires a convoluted set of restrictions that force complex modifications to the already costly design flows. In this paper, we claim that a far superior result can be achieved by moving the design-to-manufacturing interface from design rules to a higher level of abstraction based on a defined set of pre-characterized layout templates. We will demonstrate how this methodology can simplify optical proximity correction and lithography processes for sub-32nm technology nodes, along with various digital block design examples for synthesized intellectual property (IP) cores. Furthermore, with a cost-per-good-die analysis we will show that this methodology will extend economical scaling to sub-32nm technology nodes.