Transistor sizing in lithography-aware regular fabrics

Authors:
Felipe dos Santos Marranghello;Vinicius Dal Bem;André Inácio Reis;Francesc Moll;Renato Perez Ribas
Affiliations:
Federal University of Rio Grande do Sul, Porto Alegre, Brazil;Federal University of Rio Grande do Sul, Porto Alegre, Brazil;Federal University of Rio Grande do Sul, Porto Alegre, Brazil;Polytechnic University of Catalonia, Barcelona, Spain;Federal University of Rio Grande do Sul, Porto Alegre, Brazil
Venue:
Proceedings of the 24th symposium on Integrated circuits and systems design
Year:
2011

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Abstract

This paper presents an extensive analysis of transistor sizing for via-configurable regular fabrics. Different design aspects have been considered such as transistor stacking, logic gate drive strength options and critical delay paths. Performance degradation due to the use of transistor regular layout (TRL) is expected in comparison to standard cells, as a consequence of the loss in design flexibility. In this work, the speed and power consumption impact is evaluated when addressing such lithography-aware regular fabrics in digital integrated circuit design. Experimental results were obtained at the transistor level through electrical simulations, taking into account the predictive PTM 45nm CMOS parameters. The analysis presented herein can be easily extended to other technology nodes and fabrication processes.