DAGON: technology binding and local optimization by DAG matching
DAC '87 Proceedings of the 24th ACM/IEEE Design Automation Conference
Library-less synthesis for static CMOS combinational logic circuits
ICCAD '97 Proceedings of the 1997 IEEE/ACM international conference on Computer-aided design
Delay-optimal technology mapping by DAG covering
DAC '98 Proceedings of the 35th annual Design Automation Conference
Logical effort: designing fast CMOS circuits
Logical effort: designing fast CMOS circuits
DATE '99 Proceedings of the conference on Design, automation and test in Europe
Large Standard Cell Libraries and Their Impact on Layout Area and Circuit Performanc
ICCD '96 Proceedings of the 1996 International Conference on Computer Design, VLSI in Computers and Processors
Unified Theory to Build Cell-Level Transistor Networks from BDDs
SBCCI '03 Proceedings of the 16th symposium on Integrated circuits and systems design
Transduction method for design of logic cell structure
Proceedings of the 2004 Asia and South Pacific Design Automation Conference
Exact lower bound for the number of switches in series to implement a combinational logic cell
ICCD '05 Proceedings of the 2005 International Conference on Computer Design
Reducing structural bias in technology mapping
ICCAD '05 Proceedings of the 2005 IEEE/ACM International conference on Computer-aided design
Logic decomposition during technology mapping
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
A comparative study of CMOS gates with minimum transistor stacks
Proceedings of the 20th annual conference on Integrated circuits and systems design
Contributions to the evaluation of ensembles of combinational logic gates
Microelectronics Journal
Efficient method to compute minimum decision chains of Boolean functions
Proceedings of the 21st edition of the great lakes symposium on Great lakes symposium on VLSI
Transistor sizing in lithography-aware regular fabrics
Proceedings of the 24th symposium on Integrated circuits and systems design
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This paper proposes a library-free technology mapping algorithm to reduce delay in combinational circuits. The algorithm reduces the overall number of series transistors through the longest path, considering that each cell network has to obey to a maximum admitted chain. The number of series transistors is computed in a Boolean way, reducing the structural bias. The mapping algorithm is performed on a Directed Acyclic Graph (DAG) description of the circuit. Preliminary results for delay were obtained through SPICE simulations. When compared to the SIS technology mapping, the proposed method shows significant delay reductions, considering circuits mapped with different libraries.