Library-less synthesis for static CMOS combinational logic circuits
ICCAD '97 Proceedings of the 1997 IEEE/ACM international conference on Computer-aided design
Logic synthesis for large pass transistor circuits
ICCAD '97 Proceedings of the 1997 IEEE/ACM international conference on Computer-aided design
Logical effort: designing fast CMOS circuits
Logical effort: designing fast CMOS circuits
On the generation of multiplexer circuits for pass transistor logic
DATE '00 Proceedings of the conference on Design, automation and test in Europe
Low power optimization technique for BDD mapped circuits
Proceedings of the 2001 Asia and South Pacific Design Automation Conference
Transistor placement for noncomplementary digital VLSI cell synthesis
ACM Transactions on Design Automation of Electronic Systems (TODAES)
Transistor Level Synthesis for Static CMOS Combinational Circuits
GLS '99 Proceedings of the Ninth Great Lakes Symposium on VLSI
An Efficient Algorithm for Low Power Pass Transistor Logic Synthesis
ASP-DAC '02 Proceedings of the 2002 Asia and South Pacific Design Automation Conference
Unified Theory to Build Cell-Level Transistor Networks from BDDs
SBCCI '03 Proceedings of the 16th symposium on Integrated circuits and systems design
Exact lower bound for the number of switches in series to implement a combinational logic cell
ICCD '05 Proceedings of the 2005 International Conference on Computer Design
Fast disjoint transistor networks from BDDs
SBCCI '06 Proceedings of the 19th annual symposium on Integrated circuits and systems design
Exact Minimum-Width Transistor Placement for Dual and Non-dual CMOS Cells
IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences
DAG based library-free technology mapping
Proceedings of the 17th ACM Great Lakes symposium on VLSI
Optimal Layout of CMOS Functional Arrays
IEEE Transactions on Computers
A methodology for transistor-efficient supergate design
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
BDD decomposition for delay oriented pass transistor logic synthesis
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
BDS: a BDD-based logic optimization system
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Efficient transistor-level design of CMOS gates
Proceedings of the 23rd ACM international conference on Great lakes symposium on VLSI
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The performance of CMOS gates is strongly dependent on the number of transistors in series in both pull-up PMOS and pull-down NMOS networks. In this paper, two approaches presenting the minimum number of stacked devices are compared, using conventional series-parallel CMOS as a reference. The proposed analysis takes into consideration different lists of cells, including standard cell libraries used in regular (fixed library) technology mapping or functions generated by software in library-free technology mapping. The quality of the transistor networks in consideration is evaluated according to device count, worst case transistor stack, as well as logical effort of the network. The relationship between such topologies and technology mapping is also discussed.