Library-less synthesis for static CMOS combinational logic circuits
ICCAD '97 Proceedings of the 1997 IEEE/ACM international conference on Computer-aided design
Logic Design of Digital Systems
Logic Design of Digital Systems
Switching and Finite Automata Theory: Computer Science Series
Switching and Finite Automata Theory: Computer Science Series
Transistor Level Synthesis for Static CMOS Combinational Circuits
GLS '99 Proceedings of the Ninth Great Lakes Symposium on VLSI
Unified Theory to Build Cell-Level Transistor Networks from BDDs
SBCCI '03 Proceedings of the 16th symposium on Integrated circuits and systems design
Transduction method for design of logic cell structure
Proceedings of the 2004 Asia and South Pacific Design Automation Conference
Exact lower bound for the number of switches in series to implement a combinational logic cell
ICCD '05 Proceedings of the 2005 International Conference on Computer Design
Transistor-Level Optimization of Supergates
ISQED '06 Proceedings of the 7th International Symposium on Quality Electronic Design
Fast disjoint transistor networks from BDDs
SBCCI '06 Proceedings of the 19th annual symposium on Integrated circuits and systems design
A comparative study of CMOS gates with minimum transistor stacks
Proceedings of the 20th annual conference on Integrated circuits and systems design
SwitchCraft: a framework for transistor network design
SBCCI '10 Proceedings of the 23rd symposium on Integrated circuits and system design
Contributions to the evaluation of ensembles of combinational logic gates
Microelectronics Journal
Efficient transistor-level design of CMOS gates
Proceedings of the 23rd ACM international conference on Great lakes symposium on VLSI
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The number of transistors required for the implementation of a logic function is a fundamental consideration in digital VLSI design. While the determination of a series-parallel implementation can be straightforward once a simplified Boolean expression of the function is available, this may not be an optimum solution. In this paper, a methodology is developed for minimizing the number of transistors that starts from a sum-of-products expression and utilizes non-series-parallel structures. Experimental results demonstrate the efficiency of the approach.