Graph-Based Algorithms for Boolean Function Manipulation
IEEE Transactions on Computers
Leakage control with efficient use of transistor stacks in single threshold CMOS
Proceedings of the 36th annual ACM/IEEE Design Automation Conference
Prelayout estimation of individual wire lengths
IEEE Transactions on Very Large Scale Integration (VLSI) Systems - System Level Design
Algorithms for VLSI Physical Design Automation
Algorithms for VLSI Physical Design Automation
Transistor Level Synthesis for Static CMOS Combinational Circuits
GLS '99 Proceedings of the Ninth Great Lakes Symposium on VLSI
Timing Verification and the Timing Analysis program
DAC '82 Proceedings of the 19th Design Automation Conference
C5M-a control-logic layout synthesis system for high-performance microprocessors
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Exact lower bound for the number of switches in series to implement a combinational logic cell
ICCD '05 Proceedings of the 2005 International Conference on Computer Design
DAG based library-free technology mapping
Proceedings of the 17th ACM Great Lakes symposium on VLSI
A methodology for transistor-efficient supergate design
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Contributions to the evaluation of ensembles of combinational logic gates
Microelectronics Journal
Efficient transistor-level design of CMOS gates
Proceedings of the 23rd ACM international conference on Great lakes symposium on VLSI
| Hi-index | 4.10 |
Over the years, it has become commonplace to perform various forms of manual intervention ondesigns generated using automated flows. The quest to overcome the limitations of standard-cell-based design methods leads naturally to the creation of new design- and context-specific cells驴designated flex cellsýduring the process of optimizing a given digital design. Flex cell驴based design optimization automates the creation of tactical cells.The flex-cell approach, either alone or in combination with standard cells, provides an optimally tuned set of building blocks for the target IC design, which measures optimality against accepted and quantifiably definable metrics such as clock speed, die size, and power consumption.By allowing manipulation of the transistor-level structures, flex cells open up a new dimension in theoptimization of automatically created designs.