Transistor level micro-placement and routing for two-dimensional digital VLSI cell synthesis
ISPD '99 Proceedings of the 1999 international symposium on Physical design
Technology mapping for high-performance static CMOS and pass transistor logic designs
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Technology mapping algorithms for domino logic
ACM Transactions on Design Automation of Electronic Systems (TODAES)
Accurate pre-layout estimation of standard cell characteristics
Proceedings of the 41st annual Design Automation Conference
Technology mapping for SOI domino logic incorporating solutions for the parasitic bipolar effect
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Cell-based interconnect migration by hierarchical optimization
Integration, the VLSI Journal
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In high-end microprocessors, control-logic timing can gate the cycle time, but control logic is specified late and changes often. Custom design is too time consuming for control implementation, and application specific integrated circuit (ASIC)-like methods have difficulty achieving the required performance/area targets. In this paper, we describe C5M, a new layout system for high-performance control logic which has been successfully used in the design of a recent 400 MHz IBM processor. Results from this design are used to show that C5M achieves near custom quality with high productivity and predictability