CELLERITY: a fully automatic layout synthesis system for standard cell libraries
DAC '97 Proceedings of the 34th annual Design Automation Conference
Migration: a new technique to improve synthesized designs through incremental customization
DAC '98 Proceedings of the 35th annual Design Automation Conference
Gradient-based optimization of custom circuits using a static-timing formulation
Proceedings of the 36th annual ACM/IEEE Design Automation Conference
Architecting ASIC libraries and flows in nanometer era
Proceedings of the 40th annual Design Automation Conference
C5M-a control-logic layout synthesis system for high-performance microprocessors
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Performance-constrained different cell count minimization for continuously-sized circuits
Proceedings of the conference on Design, automation and test in Europe
Efficient lookahead routing and header compression for multicasting in networks-on-chip
Proceedings of the 6th ACM/IEEE Symposium on Architectures for Networking and Communications Systems
ORION 2.0: a fast and accurate NoC power and area model for early-stage design space exploration
Proceedings of the Conference on Design, Automation and Test in Europe
ACM Transactions on Architecture and Code Optimization (TACO)
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With the advent of deep-submicron technologies, it has become essential to model the impact of physical/layout effects up front in all design flows \citeITRS02. The effect of layout parasitics is considerable even at the intra-cell level in standard cells. Hence, it has become critically important for any transistor-level optimization to consider the effect of these layout parasitics as an integral part of the optimization process. However, since it is not computationally feasible for the actual layout to be a part of any such optimization procedures, we propose a technique that estimates cell layout characteristics without actually performing the layout and subsequent extraction steps. We demonstrate in this work that it is indeed feasible to estimate the layout effects to get timing characteristics that are on average within about 1.5\% of post-layout timing and that the technique is thousands of times faster than the actual creation of layout.