Gate-size selection for standard cell libraries
Proceedings of the 1998 IEEE/ACM international conference on Computer-aided design
Optimal P/N width ratio selection for standard cell libraries
ICCAD '99 Proceedings of the 1999 IEEE/ACM international conference on Computer-aided design
Accurate pre-layout estimation of standard cell characteristics
Proceedings of the 41st annual Design Automation Conference
Mathematical Programming: Series A and B
Fast and exact simultaneous gate and wire sizing by Lagrangian relaxation
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Hi-index | 0.00 |
A continuously-sized circuit resulting from transistor sizing consists of gates with large variety of sizes. In this paper, we first provide a formal formulation of performance-constrained different cell count minimization problem, and then propose an effective hill-climbing heuristic which iteratively minimizes the number of cells under performance constraints such as area, delay and power. To the best of our knowledge, this is the first attempt to address the different cell count minimization problem.