Logical effort: designing for speed on the back of an envelope
Proceedings of the 1991 University of California/Santa Cruz conference on Advanced research in VLSI
Design methodology for the S/390 parallel enterprise server G4 microprocessors
IBM Journal of Research and Development - Special issue: IBM S/390 G3 and G4
DATE '99 Proceedings of the conference on Design, automation and test in Europe
Optimal P/N width ratio selection for standard cell libraries
ICCAD '99 Proceedings of the 1999 IEEE/ACM international conference on Computer-aided design
Transformational placement and synthesis
DATE '00 Proceedings of the conference on Design, automation and test in Europe
Logic Synthesis and Verification
Logical and physical design: a flow perspective
Logic Synthesis and Verification
Gain-based technology mapping for discrete-size cell libraries
Proceedings of the 40th annual Design Automation Conference
Quality of EDA CAD Tools: Definitions, Metrics and Directions
ISQED '00 Proceedings of the 1st International Symposium on Quality of Electronic Design
Fast Comparisons of Circuit Implementations
Proceedings of the conference on Design, automation and test in Europe - Volume 2
An efficient surface-based low-power buffer insertion algorithm
Proceedings of the 2005 international symposium on Physical design
Logical effort based technology mapping
Proceedings of the 2004 IEEE/ACM International conference on Computer-aided design
Gate sizing for cell library-based designs
Proceedings of the 44th annual Design Automation Conference
Performance-constrained different cell count minimization for continuously-sized circuits
Proceedings of the conference on Design, automation and test in Europe
PaRS: fast and near-optimal grid-based cell sizing for library-based design
Proceedings of the 2008 IEEE/ACM International Conference on Computer-Aided Design
Gate sizing for cell-library-based designs
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
IBM eServer z900 high-frequency microprocessor technology, circuits, and design methodology
IBM Journal of Research and Development
PaRS: parallel and near-optimal grid-based cell sizing for library-based design
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Fast comparisons of circuit implementations
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Approximation scheme for restricted discrete gate sizing targeting delay minimization
Journal of Combinatorial Optimization
Compiler-in-the-loop exploration during datapath synthesis for higher quality delay-area trade-offs
ACM Transactions on Design Automation of Electronic Systems (TODAES) - Special section on adaptive power management for energy and temperature-aware computing systems
Impact of range and precision in technology on cell-based design
Proceedings of the International Conference on Computer-Aided Design
VLSI Design - Special issue on New Algorithmic Techniques for Complex EDA Problems
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