A delay model for logic synthesis of continuously-sized networks
ICCAD '95 Proceedings of the 1995 IEEE/ACM international conference on Computer-aided design
Wire segmenting for improved buffer insertion
DAC '97 Proceedings of the 34th annual Design Automation Conference
DAC '98 Proceedings of the 35th annual Design Automation Conference
A fast fanout optimization algorithm for near-continuous buffer libraries
DAC '98 Proceedings of the 35th annual Design Automation Conference
Buffer insertion for noise and delay optimization
DAC '98 Proceedings of the 35th annual Design Automation Conference
Gate-size selection for standard cell libraries
Proceedings of the 1998 IEEE/ACM international conference on Computer-aided design
Scaling of stack effect and its application for leakage reduction
ISLPED '01 Proceedings of the 2001 international symposium on Low power electronics and design
Closed form solutions to simultaneous buffer insertion/sizing and wire sizing
ACM Transactions on Design Automation of Electronic Systems (TODAES)
Simultaneous gate sizing and fanout optimization
Proceedings of the 2000 IEEE/ACM international conference on Computer-aided design
The scaling challenge: can correct-by-construction design help?
Proceedings of the 2003 international symposium on Physical design
Wiresizing with Buffer Placement and Sizing for Power-Delay Tradeoffs
VLSID '96 Proceedings of the 9th International Conference on VLSI Design: VLSI in Mobile Communication
Simultaneous Routing and Buffer Insertion for High Performance Interconnect
GLSVLSI '96 Proceedings of the 6th Great Lakes Symposium on VLSI
Gate Sizing and Buffer Insertion using Economic Models for Power Optimization
VLSID '04 Proceedings of the 17th International Conference on VLSI Design
Design and CAD Challenges in sub-90nm CMOS Technologies
Proceedings of the 2003 IEEE/ACM international conference on Computer-aided design
Power-Optimal Simultaneous Buffer Insertion/Sizing and Wire Sizing
Proceedings of the 2003 IEEE/ACM international conference on Computer-aided design
Proceedings of the 2004 Asia and South Pacific Design Automation Conference
A quadratic programming approach to simultaneous buffer insertion/sizing and wire sizing
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Fast and exact simultaneous gate and wire sizing by Lagrangian relaxation
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Simultaneous routing and buffer insertion with restrictions on buffer locations
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Simultaneous driver sizing and buffer insertion using a delay penalty estimation technique
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Repeater scaling and its impact on CAD
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Zero skew clock-tree optimization with buffer insertion/sizing and wire sizing
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Fast dual-vdd buffering based on interconnect prediction and sampling
Proceedings of the 2007 international workshop on System level interconnect prediction
An efficient low-power buffer insertion with time and area constraints
ICC'10 Proceedings of the 14th WSEAS international conference on Circuits
GlitchLess: dynamic power minimization in FPGAs through edge alignment and glitch filtering
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Low-energy-transmission of data on submicron interconnects
WSEAS TRANSACTIONS on COMMUNICATIONS
Revisiting automated physical synthesis of high-performance clock networks
ACM Transactions on Design Automation of Electronic Systems (TODAES)
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Buffer insertion is an important technique used to achieve timing closure in high performance VLSI designs. As the number of buffers in ASIC designs has increased with process scaling, the power con-sumption of buffers has become a critical concern. In this paper, we present an efficient algorithm that performs van Ginneken style buffer insertion on RC trees and minimizes the total power con-sumption under a given delay constraint. Our algorithm is based on a formulation that uses a buffer library consisting of continuous buffer sizes. We construct solution candidates in the form of surfaces in the 3-D delay, capacitance and power (DCP) space and show the mecha-nisms to propagate and merge them in the interconnect tree. Instead of a single minimal power solution, the algorithm produces an entire DCP surface from which a suitable solution point can be selected. We also present a post-processing step where buffers with continu-ous (non-standard) sizes are snapped to discrete size values corre-sponding to the buffers in a given library. The proposed algorithm has a worst-case runtime complexity that is polynomial (quadratic) in the number of possible buffer locations. We implemented and tested our proposed algorithm on a number of large benchmark nets and observed that our method produces a speedup in runtime of 5-6X in comparison with previous power aware buffer insertion methods.