RC interconnect synthesis—a moment fitting approach
ICCAD '94 Proceedings of the 1994 IEEE/ACM international conference on Computer-aided design
A sequential quadratic programming approach to concurrent gate and wire sizing
ICCAD '95 Proceedings of the 1995 IEEE/ACM international conference on Computer-aided design
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ACM Transactions on Design Automation of Electronic Systems (TODAES)
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DAC '96 Proceedings of the 33rd annual Design Automation Conference
Optimal wire-sizing formula under the Elmore delay model
DAC '96 Proceedings of the 33rd annual Design Automation Conference
Optimal non-uniform wire-sizing under the Elmore delay model
Proceedings of the 1996 IEEE/ACM international conference on Computer-aided design
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ISLPED '96 Proceedings of the 1996 international symposium on Low power electronics and design
Optimal wiresizing under the distributed Elmore delay model
ICCAD '93 Proceedings of the 1993 IEEE/ACM international conference on Computer-aided design
Wire segmenting for improved buffer insertion
DAC '97 Proceedings of the 34th annual Design Automation Conference
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DAC '97 Proceedings of the 34th annual Design Automation Conference
Optimal shape function for a bi-directional wire under Elmore delay model
ICCAD '97 Proceedings of the 1997 IEEE/ACM international conference on Computer-aided design
EWA: exact wiring-sizing algorithm
Proceedings of the 1997 international symposium on Physical design
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Proceedings of the 1997 international symposium on Physical design
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Proceedings of the 1997 international symposium on Physical design
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EDTC '97 Proceedings of the 1997 European conference on Design and Test
MCMC '96 Proceedings of the 1996 IEEE Multi-Chip Module Conference (MCMC '96)
A quadratic programming approach to simultaneous buffer insertion/sizing and wire sizing
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
An efficient and optimal algorithm for simultaneous buffer and wire sizing
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
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VLSID '03 Proceedings of the 16th International Conference on VLSI Design
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Proceedings of the 2005 international symposium on Physical design
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Proceedings of the 2005 international symposium on Physical design
Proceedings of the 42nd annual Design Automation Conference
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Proceedings of the 2005 Asia and South Pacific Design Automation Conference
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Operations Research
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Proceedings of the 2008 international symposium on Physical design
Logic gates as repeaters (LGR) for area-efficient timing optimization
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Elmor model-based algorithm to select optimal connections on the clock tree
Automation and Remote Control
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IEEE Transactions on Circuits and Systems Part I: Regular Papers
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Shedding physical synthesis area bloat
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In this paper, we consider the delay minimization problem of an interconnect wire by simultaneously considering buffer insertion, buffer sizing and wire sizing. We consider three cases, namely using no buffer (i.e., wire sizing alone), using a given number of buffers, and using the optimal number of buffers. We provide elegant closed form optimal solutions for all three problems. These closed form solutions are useful in early stages of the VLSI design flow such as logic synthesis and floorplanning.