Closed form solutions to simultaneous buffer insertion/sizing and wire sizing
ACM Transactions on Design Automation of Electronic Systems (TODAES)
An Efficient Hierarchical Timing-Driven Steiner Tree Algorithm for Global Routing
ASP-DAC '02 Proceedings of the 2002 Asia and South Pacific Design Automation Conference
ICCD '00 Proceedings of the 2000 IEEE International Conference on Computer Design: VLSI in Computers & Processors
An efficient hierarchical timing-driven Steiner tree algorithm for global routing
Integration, the VLSI Journal
CNB: a critical-network-based timing optimization method for standard cell global routing
Journal of Computer Science and Technology
Geometric programming for circuit optimization
Proceedings of the 2005 international symposium on Physical design
Closed form solution for optimal buffer sizing using the Weierstrass elliptic function
ASP-DAC '06 Proceedings of the 2006 Asia and South Pacific Design Automation Conference
Wire sizing with scattering effect for nanoscale interconnection
ASP-DAC '06 Proceedings of the 2006 Asia and South Pacific Design Automation Conference
UTACO: a unified timing and congestion optimizing algorithm for standard cell global routing
ASP-DAC '03 Proceedings of the 2003 Asia and South Pacific Design Automation Conference
Digital Circuit Optimization via Geometric Programming
Operations Research
Wire shaping of RLC interconnects
Integration, the VLSI Journal
Fast interconnect synthesis with layer assignment
Proceedings of the 2008 international symposium on Physical design
Proceedings of the 2009 International Conference on Computer-Aided Design
Clock skew optimization considering complicated power modes
Proceedings of the Conference on Design, Automation and Test in Europe
Proceedings of the 16th Asia and South Pacific Design Automation Conference
An optimal algorithm of adjustable delay buffer insertion for solving clock skew variation problem
Proceedings of the 50th Annual Design Automation Conference
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In this paper, we consider the problem of interconnect delay minimization by simultaneous buffer and wire sizing under the Elmore delay model. We first present a polynomial time algorithm SBWS to minimize the delay of an interconnect wire. Previously, no polynomial time algorithm for the problem has been reported in the literature. SBWS is an iterative algorithm with guaranteed convergence to the optimal solution. It runs in quadratic time and uses constant memory for computation. Experimental results show that SBWS is extremely efficient in practice. For example, for an interconnect of 10000 segments and buffers, the CPU time is only 0.255 s. We then extend our result to handle interconnect trees. We present an algorithm SBWS-T which always gives the optimal solution. Experimental results show that SBWS-T is faster than the greedy wire sizing algorithm in practice