Buffered Steiner tree construction with wire sizing for interconnect layout optimization
Proceedings of the 1996 IEEE/ACM international conference on Computer-aided design
Performance optimization of VLSI interconnect layout
Integration, the VLSI Journal
Simultaneous buffer and wire sizing for performance and power optimization
ISLPED '96 Proceedings of the 1996 international symposium on Low power electronics and design
Timing optimization for multi-source nets: characterization and optimal repeater insertion
DAC '97 Proceedings of the 34th annual Design Automation Conference
Wire segmenting for improved buffer insertion
DAC '97 Proceedings of the 34th annual Design Automation Conference
Closed form solution to simultaneous buffer insertion/sizing and wire sizing
Proceedings of the 1997 international symposium on Physical design
Buffer insertion for noise and delay optimization
DAC '98 Proceedings of the 35th annual Design Automation Conference
Buffer insertion with accurate gate and interconnect delay computation
Proceedings of the 36th annual ACM/IEEE Design Automation Conference
Simultaneous Routing and Buffer Insertion for High Performance Interconnect
GLSVLSI '96 Proceedings of the 6th Great Lakes Symposium on VLSI
A quadratic programming approach to simultaneous buffer insertion/sizing and wire sizing
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
An efficient and optimal algorithm for simultaneous buffer and wire sizing
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Minimum-buffered routing of non-critical nets for slew rate and reliability control
Proceedings of the 2001 IEEE/ACM international conference on Computer-aided design
An O(bn^2) Time Algorithm for Optimal Buffer Insertion with b Buffer Types
Proceedings of the conference on Design, Automation and Test in Europe - Volume 2
Making fast buffer insertion even faster via approximation techniques
Proceedings of the 2005 Asia and South Pacific Design Automation Conference
MeshWorks: an efficient framework for planning, synthesis and optimization of clock mesh networks
Proceedings of the 2008 Asia and South Pacific Design Automation Conference
Meshworks: a comprehensive framework for optimized clock mesh network synthesis
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
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Buffer insertion has become a critical optimization technique in high performance design. Perhaps the most prevalent buffer insertion technique is Van Ginneken's dynamic programming algorithm. Although very effective, the algorithm has time complexity that is quadratic in terms of the input buffer library size. Consequently, to achieve an efficient algorithm, it is critical that the buffer library used by the tool be relatively small, containing a subset of the most effective buffers. We propose a new algorithm for selecting a buffer library from all the buffers available in the technology, thereby permitting efficient buffer insertion. We show that the smaller buffer libraries constructed by our algorithm result in little loss in solution quality while speeding up the buffer insertion algorithm by orders of magnitude.