Buffered Steiner tree construction with wire sizing for interconnect layout optimization

Authors:
Takumi Okamoto;Jason Cong
Affiliations:
C&C Research Laboratories, NEC Corp., Kawasaki 216, Japan;Dept. of Computer Science, Univ. of California, Los Angeles, CA
Venue:
Proceedings of the 1996 IEEE/ACM international conference on Computer-aided design
Year:
1997

Citing 14
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Abstract

This paper presents an efficient algorithm for buffered Steiner tree construction with wire sizing. Given a source and n sinks of a signal net, with given positions and a required arrival time associated with each sink, the algorithm finds a Steiner tree with buffer insertion and wire sizing so that the required arrival time (or timing slack) at the source is maximized. The unique contribution of our algorithm is that it performs Steiner tree construction, buffer insertion, and wire sizing simultaneously with consideration of both critical delay and total capacitance minimization by combining the performance-driven A-tree construction and dynamic programming based buffer insertion and wire sizing, while tree construction and the other delay minimization techniques were carried out independently in the past. Experimental results show the effectiveness of our approach.