Buffered Steiner tree construction with wire sizing for interconnect layout optimization
Proceedings of the 1996 IEEE/ACM international conference on Computer-aided design
Simultaneous buffer and wire sizing for performance and power optimization
ISLPED '96 Proceedings of the 1996 international symposium on Low power electronics and design
Buffer insertion with accurate gate and interconnect delay computation
Proceedings of the 36th annual ACM/IEEE Design Automation Conference
Zero-skew clock tree construction by simultaneous routing, wire sizing and buffer insertion
ISPD '00 Proceedings of the 2000 international symposium on Physical design
Statistical timing analysis driven post-silicon-tunable clock-tree synthesis
ICCAD '05 Proceedings of the 2005 IEEE/ACM International conference on Computer-aided design
Variability-driven formulation for simultaneous gate sizing and post-silicon tunability allocation
Proceedings of the 2007 international symposium on Physical design
Unified adaptivity optimization of clock and logic signals
Proceedings of the 2007 IEEE/ACM international conference on Computer-aided design
An efficient and optimal algorithm for simultaneous buffer and wire sizing
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Zero skew clock-tree optimization with buffer insertion/sizing and wire sizing
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
General skew constrained clock network sizing based on sequential linear programming
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
An efficient phase detector connection structure for the skew synchronization system
Proceedings of the 47th Design Automation Conference
Proceedings of the 16th Asia and South Pacific Design Automation Conference
Proceedings of the 16th Asia and South Pacific Design Automation Conference
Fault-tolerant 3D clock network
Proceedings of the 48th Design Automation Conference
Synthesis of an efficient controlling structure for post-silicon clock skew minimization
Proceedings of the International Conference on Computer-Aided Design
Assignment of adjustable delay buffers for clock skew minimization in multi-voltage mode designs
Proceedings of the 23rd ACM international conference on Great lakes symposium on VLSI
An optimal algorithm of adjustable delay buffer insertion for solving clock skew variation problem
Proceedings of the 50th Annual Design Automation Conference
Low-power timing closure methodology for ultra-low voltage designs
Proceedings of the International Conference on Computer-Aided Design
| Hi-index | 0.00 |
In synchronous circuit designs, clock skew is difficult to minimize because a single physical layout of a clock tree must satisfy multiple constraints in a complicated power mode environment where certain modules may operate with different voltages. In this paper, we use Adjustable Delay Buffers (ADB) whose delays can be tuned or adjusted to minimize clock skew under different power modes. Assuming that the positions of k ADBs are already determined, we propose a linear-time optimal algorithm which assigns the values of ADBs so that the skew is optimal among all possible ADB assignments. We also propose an efficient heuristic to determine good positions for ADBs. Our results show significant improvement when compared to cases without ADBs.