Minimum padding to satisfy short path constraints
ICCAD '93 Proceedings of the 1993 IEEE/ACM international conference on Computer-aided design
Energy minimization using multiple supply voltages
IEEE Transactions on Very Large Scale Integration (VLSI) Systems - Special issue on low power electronics and design
Clock period minimization with minimum delay insertion
Proceedings of the 44th annual Design Automation Conference
Proceedings of the 2009 International Conference on Computer-Aided Design
Clock skew optimization considering complicated power modes
Proceedings of the Conference on Design, Automation and Test in Europe
Proceedings of the 16th Asia and South Pacific Design Automation Conference
Designing ultra-low voltage logic
Proceedings of the 17th IEEE/ACM international symposium on Low-power electronics and design
Useful-skew clock optimization for multi-power mode designs
Proceedings of the International Conference on Computer-Aided Design
Bidirectional Single-Supply Level Shifter with Wide Voltage Range for Efficient Power Management
VLSID '12 Proceedings of the 2012 25th International Conference on VLSI Design
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As the supply voltage is down to the ultra-low voltage (ULV) level, timing closure becomes a serious challenge in the use of multiple power modes. Due to a wide voltage range, a very huge clock skew may occur among different power modes. To reduce this huge clock skew, the conventional power-mode-aware clock tree often suffers from a huge overhead on power consumption. Moreover, at the ULV level, since the setup time and the hold time of each register dramatically increase, the number of timing violations also increases greatly. However, the existing minimum padding technique cannot fix hold time violations in multiple power modes. Based on those two observations, in this paper, we propose a low-power timing closure methodology, which incorporates the synthesis of clock tree and data path, for multi-power-mode ULV designs. Our low-power timing closure methodology has two main approaches. First, we use multiple power modes to build a power-mode-aware clock tree for reducing clock skew with very small power consumption. Second, we propose the first multi-power-mode minimum padding technique to fix all the hold time violations in all the power modes simultaneously. Experimental results consistently show that the integration of both approaches yields the best results.