Clock skew optimization considering complicated power modes

Authors:
Chiao-Ling Lung;Zi-Yi Zeng;Chung-Han Chou;Shih-Chieh Chang
Affiliations:
National Tsing-Hua University, HsinChu, Taiwan and Industrial Technology Research Institute, HsinChu, Taiwan;National Tsing-Hua University, HsinChu, Taiwan;National Tsing-Hua University, HsinChu, Taiwan;National Tsing-Hua University, HsinChu, Taiwan
Venue:
Proceedings of the Conference on Design, Automation and Test in Europe
Year:
2010

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Abstract

To conserve energy, a design which utilizes different power modes has been widely adopted. However, when a design has many different power modes, clock tree optimization (CTO) becomes very difficult. In this paper, we propose a two-level power-mode-aware CTO methodology. Among all different power modes, the chip-level CTO globally reduces clock skew among modules, whereas the module-level CTO reduces clock skew within a single module. Our experimental results show that the power-mode-aware CTO can achieve significant improvement in the worst-case condition with only a minor penalty in area.