A clustering-based optimization algorithm in zero-skew routings
DAC '93 Proceedings of the 30th international Design Automation Conference
Reuse methodology manual: for system-on-a-chip designs
Reuse methodology manual: for system-on-a-chip designs
System-on-a-Chip: Design and Test
System-on-a-Chip: Design and Test
A 800 MHz System-on-Chip for Wireless Infrastructure Applications
VLSID '04 Proceedings of the 17th International Conference on VLSI Design
An efficient merging scheme for prescribed skew clock routing
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Clock skew optimization considering complicated power modes
Proceedings of the Conference on Design, Automation and Test in Europe
A dual-MST approach for clock network synthesis
Proceedings of the 2010 Asia and South Pacific Design Automation Conference
A new clock network synthesizer for modern VLSI designs
Integration, the VLSI Journal
Clock tree resynthesis for multi-corner multi-mode timing closure
Proceedings of the 2014 on International symposium on physical design
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A key problem that arises in System-on-a-Chip (SOC) designs of today is the Chip-level Clock Tree Synthesis (CCTS). CCTS is done by merging all the clock trees belonging to different IPs per chip specifications. A primary requirement of CCTS is to balance the sub-clock-trees belonging to different IPs such that the entire tree has a small skew across all process corners. This helps in timing closure across all the design corners. Another important requirement of CCTS is to reduce clock divergence between IPs that have critical timing paths between them, thereby reducing maximum possible clock skew in the critical paths and thus improves yield. In this work, we propose effective CCTS algorithms to simultaneously reduce multi-corner skew and clock divergence. To the best of our knowledge, this is the first work that attempts to solve this practically important problem. Experimental results on several testcases indicate that our methods achieve 10%-31%(20% on average) clock divergence reduction and between 16--64ps skew reduction (1.6%-6.4% of cycle time for a 1GHz clock) with less than 0.5% increase in buffer area/wirelength compared to existing CTS algorithms.