IEEE Transactions on Computers
Performance analysis and optimization of asynchronous circuits
Performance analysis and optimization of asynchronous circuits
Post-layout optimization for deep submicron design
DAC '96 Proceedings of the 33rd annual Design Automation Conference
Maximizing performance by retiming and clock skew scheduling
Proceedings of the 36th annual ACM/IEEE Design Automation Conference
Clock skew scheduling for improved reliability via quadratic programming
ICCAD '99 Proceedings of the 1999 IEEE/ACM international conference on Computer-aided design
Timing driven force directed placement with physical net constraints
Proceedings of the 2003 international symposium on Physical design
Optimal useful clock skew scheduling in the presence of variations using robust ILP formulations
Proceedings of the 2006 IEEE/ACM international conference on Computer-aided design
ECO timing optimization using spare cells
Proceedings of the 2007 IEEE/ACM international conference on Computer-aided design
Robust chip-level clock tree synthesis for SOC designs
Proceedings of the 45th annual Design Automation Conference
Delay-optimal simultaneous technology mapping and placement with applications to timing optimization
Proceedings of the 2008 IEEE/ACM International Conference on Computer-Aided Design
Static Timing Analysis for Nanometer Designs: A Practical Approach
Static Timing Analysis for Nanometer Designs: A Practical Approach
Obstacle-aware clock-tree shaping during placement
Proceedings of the 2011 international symposium on Physical design
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Zero skew clock-tree optimization with buffer insertion/sizing and wire sizing
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
An exact zero-skew clock routing algorithm
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
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With aggressive technology scaling and complex design scenarios, timing closure has become a challenging and tedious job for the designers. Timing violations persist for multi- corner, multi-mode designs in the deep-routing stage although careful optimization has been applied at every step after synthesis. Useful clock skew optimization has been suggested as an effective way to achieve design convergence and timing closure. Existing approaches on useful skew optimization (i) calculate clock skew at sequential elements before the actual tree is synthesized, and (ii) do not account for the implementability of the calculated schedules at the later stages of design cycle. Our approach is based on a skew scheduling engine which works on an already built clock tree. The output of the engine is a set of positive and negative offsets which translate to the delay and accelerations respectively in clock arrival at the clock tree pins. A novel algorithm is presented to accurately realize these offsets in the clock tree. Experimental results on large-scale industrial designs demonstrate that our approach achieves respectively 57%, 12% and 42% average improvement in total negative slack (TNS), worst negative slack (WNS) and failure-end-point (FEP) with an average overhead of 26% in clock tree area.