Performance analysis based on timing simulation
DAC '94 Proceedings of the 31st annual Design Automation Conference
Automatic synthesis of extended burst-mode circuits using generalized C-elements
EURO-DAC '96/EURO-VHDL '96 Proceedings of the conference on European design automation
Timing analysis for synthesis in microprocessor interface design
ISSS '94 Proceedings of the 7th international symposium on High-level synthesis
Practical applications of an efficient time separation of events algorithm
ICCAD '93 Proceedings of the 1993 IEEE/ACM international conference on Computer-aided design
The practical application of retiming to the design of high-performance systems
ICCAD '93 Proceedings of the 1993 IEEE/ACM international conference on Computer-aided design
Approximate algorithms for time separation of events
ICCAD '97 Proceedings of the 1997 IEEE/ACM international conference on Computer-aided design
Analyzing Asynchronous Pipeline Schedules
International Journal of Parallel Programming
A timing-driven design and validation methodology for embedded real-time systems
ACM Transactions on Design Automation of Electronic Systems (TODAES)
Efficient algorithms for optimum cycle mean and optimum cost to time ratio problems
Proceedings of the 36th annual ACM/IEEE Design Automation Conference
Performance analysis and optimization of latency insensitive systems
Proceedings of the 37th Annual Design Automation Conference
A methodology for correct-by-construction latency insensitive design
ICCAD '99 Proceedings of the 1999 IEEE/ACM international conference on Computer-aided design
Reducing probabilistic timed petri nets for asynchronous architectural analysis
Proceedings of the 8th ACM/IEEE international workshop on Timing issues in the specification and synthesis of digital systems
Proceedings of the 2000 IEEE/ACM international conference on Computer-aided design
An Algorithm for Exact Bounds on the Time Separation of Events in Concurrent Systems
IEEE Transactions on Computers
Maximum Time Separation of Events in Cyclic Systems with Linear and Latest Timing Constraints
FMCAD '98 Proceedings of the Second International Conference on Formal Methods in Computer-Aided Design
On the Performance Evaluation of Fully Asynchronous Processor Architectures
MASCOTS '95 Proceedings of the 3rd International Workshop on Modeling, Analysis, and Simulation of Computer and Telecommunication Systems
Performance Analysis of Asynchronous Circuits Using Markov Chains
Concurrency and Hardware Design, Advances in Petri Nets
Stretching quasi delay insensitivity by means of extended isochronic forks
ASYNC '95 Proceedings of the 2nd Working Conference on Asynchronous Design Methodologies
A single-rail re-implementation of a DCC error detector using a generic standard-cell library
ASYNC '95 Proceedings of the 2nd Working Conference on Asynchronous Design Methodologies
High-Performance Asynchronous Pipeline Circuits
ASYNC '96 Proceedings of the 2nd International Symposium on Advanced Research in Asynchronous Circuits and Systems
ASYNC '99 Proceedings of the 5th International Symposium on Advanced Research in Asynchronous Circuits and Systems
Symbolic Time Separation of Events
ASYNC '99 Proceedings of the 5th International Symposium on Advanced Research in Asynchronous Circuits and Systems
Bounding Average Time Separations of Events in Stochastic Timed Petri Nets with Choice
ASYNC '99 Proceedings of the 5th International Symposium on Advanced Research in Asynchronous Circuits and Systems
Retiming for Wire Pipelining in System-On-Chip
Proceedings of the 2003 IEEE/ACM international conference on Computer-aided design
Multi-Domain Clock Skew Scheduling
Proceedings of the 2003 IEEE/ACM international conference on Computer-aided design
Experimental analysis of the fastest optimum cycle ratio and mean algorithms
ACM Transactions on Design Automation of Electronic Systems (TODAES)
Optimization of NULL convention self-timed circuits
Integration, the VLSI Journal
Efficient performance analysis of asynchronous systems based on periodicity
CODES+ISSS '05 Proceedings of the 3rd IEEE/ACM/IFIP international conference on Hardware/software codesign and system synthesis
Optimal wire retiming without binary search
Proceedings of the 2004 IEEE/ACM International conference on Computer-aided design
Convergence-provable statistical timing analysis with level-sensitive latches and feedback loops
ASP-DAC '06 Proceedings of the 2006 Asia and South Pacific Design Automation Conference
Efficient incremental clock latency scheduling for large circuits
Proceedings of the conference on Design, automation and test in Europe: Proceedings
Reasoning about synchronization in GALS systems
Formal Methods in System Design
Leveraging protocol knowledge in slack matching
Proceedings of the 2006 IEEE/ACM international conference on Computer-aided design
Clock skew scheduling with race conditions considered
ACM Transactions on Design Automation of Electronic Systems (TODAES)
Topology-based optimization of maximal sustainable throughput in a latency-insensitive system
Proceedings of the 44th annual Design Automation Conference
Global critical path: a tool for system-level timing analysis
Proceedings of the 44th annual Design Automation Conference
A fast incremental clock skew scheduling algorithm for slack optimization
Proceedings of the 2008 Asia and South Pacific Design Automation Conference
Slack analysis in the system design loop
CODES+ISSS '08 Proceedings of the 6th IEEE/ACM/IFIP international conference on Hardware/Software codesign and system synthesis
Time separations of cyclic event rule systems with min-max timing constraints
Theoretical Computer Science
Performance optimization of elastic systems using buffer resizing and buffer insertion
Proceedings of the 2008 IEEE/ACM International Conference on Computer-Aided Design
Performance estimation and slack matching for pipelined asynchronous architectures with choice
Proceedings of the 2008 IEEE/ACM International Conference on Computer-Aided Design
High performance asynchronous design flow using a novel static performance analysis method
Computers and Electrical Engineering
Multi-level clustering for clock skew optimization
Proceedings of the 2009 International Conference on Computer-Aided Design
The Role of Back-Pressure in Implementing Latency-Insensitive Systems
Electronic Notes in Theoretical Computer Science (ENTCS)
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Efficient simulation of oscillatory combinational loops
Proceedings of the 47th Design Automation Conference
Multi-domain clock skew scheduling-aware register placement to optimize clock distribution network
Proceedings of the Conference on Design, Automation and Test in Europe
Accurate performance estimation for stochastic marked graphs by bottleneck regrowing
EPEW'10 Proceedings of the 7th European performance engineering conference on Computer performance engineering
A survey of the theory of min-max systems
ICIC'05 Proceedings of the 2005 international conference on Advances in Intelligent Computing - Volume Part II
The level set method for the two-sided max-plus eigenproblem
Discrete Event Dynamic Systems
Clock tree resynthesis for multi-corner multi-mode timing closure
Proceedings of the 2014 on International symposium on physical design
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This paper presents an attempt to implement an Artificial Neural System (ANS) in J, a significantly simplified and enhanced version of APL [1,2]. Neural networks are fairly straightforward to program in a language such as J.A software tool (based on C and J) for the development and simulation of neural networks is presented in this paper. it provides a rudimentary platform for implementing ANS systems.