Strategies for real-time system specification
Strategies for real-time system specification
Performance analysis and optimization of asynchronous circuits
Performance analysis and optimization of asynchronous circuits
SAC '93 Proceedings of the 1993 ACM/SIGAPP symposium on Applied computing: states of the art and practice
Specification, simulation, and verification of timing behavior
Specification, simulation, and verification of timing behavior
Efficient algorithms for interface timing verification
EURO-DAC '94 Proceedings of the conference on European design automation
Scheduling Tasks with AND/OR Precedence Constraints
SIAM Journal on Computing
Determining the minimum iteration period of an algorithm
Journal of VLSI Signal Processing Systems
Approximate algorithms for time separation of events
ICCAD '97 Proceedings of the 1997 IEEE/ACM international conference on Computer-aided design
Hardware-software co-design of embedded systems: the POLIS approach
Hardware-software co-design of embedded systems: the POLIS approach
Rate derivation and its applications to reactive, real-time embedded systems
DAC '98 Proceedings of the 35th annual Design Automation Conference
Rate analysis for embedded systems
ACM Transactions on Design Automation of Electronic Systems (TODAES)
Maintaining knowledge about temporal intervals
Communications of the ACM
Software Design Methods for Concurrent and Real-Time Systems
Software Design Methods for Concurrent and Real-Time Systems
Hardware-Software Co-Synthesis of Distributed Embedded Systems
Hardware-Software Co-Synthesis of Distributed Embedded Systems
Scheduling for Reactive Real-Time Systems
IEEE Micro
Guaranteeing Real-Time Requirements With Resource-Based Calibration of Periodic Processes
IEEE Transactions on Software Engineering
Algorithms for Interface Timing Verification
ICCD '92 Proceedings of the 1991 IEEE International Conference on Computer Design on VLSI in Computer & Processors
Managing Memory Requirements in the Synthesis of Real-Time Systems from Processing Graphs
RTAS '98 Proceedings of the Fourth IEEE Real-Time Technology and Applications Symposium
On task schedulability in real-time control systems
RTSS '96 Proceedings of the 17th IEEE Real-Time Systems Symposium
Rate derivation and its applications to reactive, real-time embedded systems
DAC '98 Proceedings of the 35th annual Design Automation Conference
Timing-driven HW/SW codesign based on task structuring and process timing simulation
CODES '99 Proceedings of the seventh international workshop on Hardware/software codesign
Timing driven co-design of networked embedded systems
ASP-DAC '00 Proceedings of the 2000 Asia and South Pacific Design Automation Conference
Proceedings of the 40th annual Design Automation Conference
A Validation Fault Model for Timing-Induced Functional Errors
ITC '01 Proceedings of the 2001 IEEE International Test Conference
Scenario-based timing verification of multiprocessor embedded applications
ACM Transactions on Design Automation of Electronic Systems (TODAES)
Thermal analysis of multiprocessor SoC applications by simulation and verification
ACM Transactions on Design Automation of Electronic Systems (TODAES)
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We address the problem of timing constraint derivation and validation for reactive and real-time embedded systems. We assume that such a system is structured into its tasks, and the structure is modeled using a task graph. Our solution uses the timing behavior committed by the environment to the system first to derive the timing constraints on the system's internal behavior and then use them to derive and validate the timing constraints on the system's external behavior. Our solution consists of the following contributions: a generalized task graph model, a comprehensive classification of timing constraints, algorithms for derivation and validation of timing constraints of the system modeled in the generalized task graph model, a codesign methodology that combines the model and the algorithms, and the implementation of this methodology in a tool called RADHA-RATAN. The main advantages of our solution are that it simplifies the problem of ensuring timing correctness of the system by reducing the complexity of the problem from system level to task level, and that it makes the codesign methodology timing-driven in that our solution makes it possible to maintain a handle on the system's timing correctness from very early stages in the system's design flow.