High level synthesis of ASICs under timing and synchronization constraints
High level synthesis of ASICs under timing and synchronization constraints
SAC '93 Proceedings of the 1993 ACM/SIGAPP symposium on Applied computing: states of the art and practice
Scheduling Tasks with AND/OR Precedence Constraints
SIAM Journal on Computing
On the models for asynchronous circuit behaviour with OR causality
Formal Methods in System Design
Static timing analysis of embedded software
DAC '97 Proceedings of the 34th annual Design Automation Conference
Hardware-software co-design of embedded systems: the POLIS approach
Hardware-software co-design of embedded systems: the POLIS approach
Rate analysis for embedded systems
ACM Transactions on Design Automation of Electronic Systems (TODAES)
A timing-driven design and validation methodology for embedded real-time systems
ACM Transactions on Design Automation of Electronic Systems (TODAES)
Software Design Methods for Concurrent and Real-Time Systems
Software Design Methods for Concurrent and Real-Time Systems
Scheduling for Reactive Real-Time Systems
IEEE Micro
Guaranteeing Real-Time Requirements With Resource-Based Calibration of Periodic Processes
IEEE Transactions on Software Engineering
RATAN: A Tool for Rate Analysis and Rate Constraint Debugging for Embedded Systems
EDTC '97 Proceedings of the 1997 European conference on Design and Test
On task schedulability in real-time control systems
RTSS '96 Proceedings of the 17th IEEE Real-Time Systems Symposium
Hardware-software co-synthesis of distributed embedded systems
Hardware-software co-synthesis of distributed embedded systems
A timing-driven design and validation methodology for embedded real-time systems
ACM Transactions on Design Automation of Electronic Systems (TODAES)
Timing-driven HW/SW codesign based on task structuring and process timing simulation
CODES '99 Proceedings of the seventh international workshop on Hardware/software codesign
Timing driven co-design of networked embedded systems
ASP-DAC '00 Proceedings of the 2000 Asia and South Pacific Design Automation Conference
Modeling and simulation of steady state and transient behaviors for emergent SoCs
Proceedings of the 14th international symposium on Systems synthesis
Large exploration for HW/SW partitioning of multirate and aperiodic real-time systems
Proceedings of the tenth international symposium on Hardware/software codesign
A Validation Fault Model for Timing-Induced Functional Errors
ITC '01 Proceedings of the 2001 IEEE International Test Conference
Journal of VLSI Signal Processing Systems
Test scenarios generation for a class of processes defined in the BPEL language
Annales UMCS, Informatica
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An embedded system (the system) continuously interacts with its environment under strict timing constraints, called the external constraints, and it is important to know how these external constraints translate to time budgets, called the internal constraints, on the tasks of the system. Knowing these time budgets reduces the complexity of the system's design and validation problem and helps the designers have a simultaneous control on the system's functional as well as temporal correctness from the beginning of the design flow. The translation is carried out by first deriving the rate of each task in the system, hence the term “rate derivation”, using the system's task structure and the rates of the input stimuli coming into the system from its environment. The derived task rates are later used to derive and validate the rest of the internal as well as external constraints. This paper proposes a general task graph model to represent the system's task structure, techniques for deriving and validating the system's timing constraints, and a hardware/software codesign methodology that puts everything together.1